PDF ACS1790T Data sheet ( Hoja de datos )

Número de pieza	ACS1790T
Descripción	PLL Frequency Synthesizer
Fabricantes	Semtech
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No Preview Available ! ADVANCED COMMUNICATIONS PRODUCT GROUP Introduction The ACS1790T is a high-performance, low phase noise, programmable frequency synthesizer with ultra-fine dynamic output frequency control. It can be used as a companion to a compatible ToPSync™ device to generate outputs locked to an external reference source or standalone for standard frequency generation for common applications. The circuit includes an integrated VCO, loop filter, phase-and-frequency detector and output dividers. The default power-up mode is definable by pin settings and once operational the ACS1790T is fully-programmable via an I2C interface. The ACS1790T requires only a low-speed external clock input for operation. When used in conjunction with a compatible ToPSync® device in a Synchronous Ethernet system the ACS1790T allows the Ethernet transmit clocks to be derived initially from the local reference oscillator and subsequently frequency-locked to an external reference source once the system is fully configured, simplifying system design and reducing component count and BOM cost. Pin Diagram 24 19 RESETB 1 OSCFSEL0 CLK OSCFSEL1 VDDD VSSD 6 ACS1790T 18 VDDA OUT1P OUT1N VSSA VSSD2 13 OUT2 7 12 ACS1790T PLL Frequency Synthesizer with Integrated VCO FINAL DATASHEET Features  Optimised for Synchronous Ethernet, SONET and SDH operation  Meets RMS jitter requirements of Gigabit Ethernet, 10 Gigabit Ethernet and OC-48 / STM- 16  Default options for 25 MHz & 125 MHz or 25 MHz & 156.25 MHz outputs at reset  High frequency LVPECL output: 10 MHz – 200 MHz, 1 ppb step  Low frequency LVCMOS output: 2 kHz – 125 MHz 1.8V, 2.5V and 3.3V operation  Very-low frequency feedback clock output for connection to ToPSync® or external PFD  Tunable over +/- 500 ppm range without loss of lock  Integrated VCO, PFD and loop filter  2.3 – 2.7 GHz VCO frequency  Typical RMS jitter performance for target application masks: OC-48, STM-16 (ANSI T1.105.03 & ITU-T G.813) 0.56 ps (12 kHz – 20 MHz) 1G Ethernet (IEEE 802.3-2008 38 & 39) 0.15 ps (637 kHz – 20 MHz) XAUI (IEEE 802.3-2008 Clause 47) 0.11 ps (1.875 MHz – 20 MHz) 10G Ethernet (IEEE 802.3-2008 53 & 54) 0.29 ps (4 MHz – 80 MHz)  Reference spurs: < -67 dBc  10, 12.8, 20 or 25 MHz input clock  Operating voltage: 3.0 - 3.6V  I2C -bus interface  Four selectable slave addresses to allow multiple devices to be used with a single controlling master  Lock detect output  Pin and register output enable control  Temperature range: -40 to 85C  4 x 4 mm QFN 24 package  Pb-Free, Halogen free, RoHS/WEEE compliant product Revision 1.0 May 2013 © Semtech Corp. Page 1 www.semtech.com 1 page ACS1790T ADVANCED COMMUNICATIONS PRODUCT GROUP Block Diagram VDDA VDDF VDDD VDDD2 LD FINAL DATASHEET OEB RESETB POWER MANAGEMENT CLK ‘R’ DIVIDER OSCFSEL0 OSCFSEL1 MODE CONTROL A0 A1 SCL SDA LOCK DETECTOR VCO ‘N’ INTEGER DIVIDER ‘K’ FRACTIONAL DIVIDER FEEDBACK DIVIDER ‘O’ DIVIDER ‘P’ DIVIDER ‘B’ DIVIDER ‘T’ DIVIDER FBCLK_ SELECT VSSA VSSF VSSD VSSD2 Figure 1 : ACS1790T Block Diagram OUT2 OUT1P OUT1N FBCLK Revision 1.0 May 2013 © Semtech Corp. Page 5 www.semtech.com 5 Page ACS1790T ADVANCED COMMUNICATIONS PRODUCT GROUP FINAL DATASHEET I2C Write Figure 4 shows the process used to write one or more registers. The operation is initiated by the host generating a start, or repeated start, condition and then writing the appropriate slave address (with bit 0 clear) followed immediately by the eight bit address of the first register to be written and then one or more data bytes containing the desired register contents. After each register write the register address pointer is automatically incremented unless it has reached the address of the highest register, 0x0A. This allows multiple consecutive registers to be written simply by sending additional data bytes. The host must generate either a stop or a repeated start condition to terminate the write operation. The ACS1790T acknowledges the slave address, and all subsequent bytes written, in accordance with the I2C specification. Figure 4 : I2C Write Operation I2C Read Figure 5 shows the process used to read one or more registers. It starts off in the same way as a register write operation, with the host writing the slave address (with bit 0 clear) followed by the address of the register to access. However, the host must then issue a repeated start condition, or optionally a stop followed by a start, followed by a write of the slave address with bit 0 set to initiate a read operation. The host can then read consecutive registers as required until generating a final stop condition. As for write operations, the auto-increment of the address stops at the last register, allowing this register to be polled with repeated reads without needing to re-write the register address. In accordance with the I2C specification, the host must acknowledge receipt of each byte read, by driving SDA low during the ninth bit time of the byte, except for the last byte that must not be acknowledged (by allowing SDA to float). This signals the ACS1790T to not drive SDA during the next bit time so that the host can generate the stop condition. Revision 1.0 May 2013 © Semtech Corp. Figure 5 : I2C Read Operation Page 11 www.semtech.com 11 Page

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