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PDF PI6LC48P0405 Data sheet ( Hoja de datos )
| Número de pieza | PI6LC48P0405 | |
| Descripción | 4-Output LVPECL Networking Clock Generator | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6LC48P0405
4-Output LVPECL Networking Clock Generator
Features
ÎÎFour differential LVPECL output pairs
ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL
single-ended clock input
ÎÎSupports the following output frequency: 125MHz
ÎÎRMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.14ps (typical)
ÎÎRMS phase jitter @ 125MHz, using a 25MHz crystal (12kHz
– 20MHz): 0.32ps (typical)
ÎÎFull 3.3V or 2.5V supply modes
ÎÎ-40°C to 85°C operating temperature
ÎÎAvailable in lead-free package: 24-TSSOP
Description
The PI6LC48P0405 is a 4-output LVPECL synthesizer optimized
to generate 125MHz clock frequencies and is a member of Peri-
com’s HiFlex family of high performance clock solutions.
The PI6LC48P0405 uses Pericom’s proprietary low phase noise
VCO technology and can achieve less than 0.32ps typical rms
phase jitter, it is ideal for Ethernet interface in all kind of sys-
tems.
Applications
ÎÎNetworking systems
Block Diagram
PLL_Bypass
XTAL_IN
XTAL_OUT
Ref_IN
IN_SEL
OSC
M_reset
Phase
Detector
VCO
M = 25 (fixed)
CLK0
CLK0#
÷5 CLK1
CLK1#
CLK2
CLK2#
CLK3
CLK3#
15-0118
1 www.pericom.com PI6LC48P0405 Rev.A
09/01/15
1 page  
PI6LC48P0405
4-Output LVPECL Networking Clock Generator
LVPECL DC Characterisitcs, (VDD = VDDO = 3.3V ± 5%, TA = -40 to 85ºC)
Symbol Parameter
Condition
VOH Output High Voltage(1)
VDD = 3.3V
VDD = 2.5V
VOL Output Low Voltage(1)
VDD = 3.3V
VDD = 2.5V
Note: 1. LVPECL Termination: Source 150ohm to GND and 100ohm across CLK and CLK#.
Min Typ Max Units
1.9
1.1
2.4
1.6
V
1.2
0.4
1.6
0.8
V
AC Electrical Characteristics
LVPECL Termination: Source 150ohm to GND and using 0.01uF ac-coupled to 50ohm to GND
AC Characterisitcs, (VDD = VDDO = 3.3V ± 5%, VDD = VDDO = 2.5V ± 5% , TA = -40 to 85ºC)
Symbol
fOUT
tsk(o)
tjit(Ø)
tR / tF
odc
Parameter
Output Frequency Range
Output Skew(1, 2)
RMS Phase Jitter,
(Random)(3)
Output Rise/Fall Time
Output Duty Cycle
Condition
125MHz,
(1.875MHz - 20MHz)
125MHz,
(12kMHz - 20MHz)
20% to 80%
Min.
112
48
Typ.
125
0.14
0.32
Max
136
70
400
52
Units
MHz
ps
ps
ps
ps
%
Note: Electrical parameters are quaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test
socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these
conditions.
Note1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.
Note2: This parameter is defined in accordance with JEDEC Standard 65.
Note3: Please refer to the Phase Noise Plots.
Phase Noise Plot
15-0118
5 www.pericom.com PI6LC48P0405 Rev.A
09/01/15
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet PI6LC48P0405.PDF ] | |
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