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Número de pieza | PI6LC4830 | |
Descripción | Network Clock Generator | |
Fabricantes | Pericom Semiconductor | |
Logotipo | ||
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No Preview Available ! PI6LC4830
HiFlexTM Network Clock Generator
Features
ÎÎ3.3V supply voltage
ÎÎ3 HCSL and 1 LVCMOS 100MHz outputs with OE/ function
ÎÎ1 LVCMOS 100/50MHz selectable
ÎÎ25MHz crystal or differential input
ÎÎLow 1ps RMS max integrated phase noise design
ÎÎPLL Bypass mode for test
ÎÎ32 lead 5x5mm TQFN package
Description
The PI6LC4830 is an LC VCO based low phase noise design
intended for the most demanding PCIe® 2.0 applications. Use
of the ultra-low noise LC VCO allows for much greater noise
margins than traditional solutions. This is ideal for noisy envi-
ronments.
Pin Configuration
PLL_Byps
REF_OUT_OE
QB_OE
QB_DIV2
VDD_PLL
IN+
IN-
VDD_REF_Out
32 31 30 29 28
1
27 26 25
24
2 23
3 22
4
GND
21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
QA1+
QA1-
VDD_Out
QA2+
QA2-
GND
QA_CMOS
VDD_OutA_SE
Block Diagram
IN_SEL
OSC
IN+
IN-
12-0238
PLL_Byps
REF_OUT_OE
REF_OUT
PLL /R
QA0:QA2
100MHz
HCSL Outputs
QA_CMOS
QA_OE
QB_CMOS
/2
QB_DIV2
QB_OE
1 PI6LC4830 Rev B
08/17/12
1 page PI6LC4830
HiFlexTM Network Clock Generator
Differential DC Input Characteristics (Over Operating Conditions)
Symbol
IIH
IIL
VCMR
VPP
Parameters
Input High
Current
Input Low
Current
IN-
IN+
IN-
IN+
Common Mode Voltage Range
Peak-to-Peak Input Voltage Swing
Conditions
VIN = VDD = 3.465V
VIN = VDD = 3.465V
VIN = 0V
VIN = 0V
Min. Typ. Max. Units
5
-45 45 uA
-5
0.5
VDD-
0.85V
V
0.15 1.3
HCSL DC Electrical Characteristics (Over Operating Conditions)
Symbol
VOH
VOL
VCROSS
Parameters
Output High Voltage
Output Low Voltage
Absolute Crossing Point Voltages
Condition
VDD_OUT = VDD -0.15V (1)
Min. Typ. Max.
660 900
150
250 550
Units
mV
D VCROSS
Total variation of VCROSS overall edges
140
IOH
Output High Current w/ 475-Ohm resistor.
Connected between IREF pin and GND
14 mA
Note:
1. This voltage drop is to account for the voltage across the series resistor in the layout guidelines.
HCSL AC Output Switching Characteristics(1,2,3) (Over Operating Conditions)
Symbol
Parameters
Min Typ Max. Units Notes
ferror
Frequency Synthesis Error
0 ppm
Trise / Tfall
Rise and Fall Time (measured between 0.175V to 0.525V)
175 250 700
2
ΔTrise / ΔTfall Rise and Fall Time Variation
7
125 ps
2
Tskew
Output-to-Output Skew
20 100
3
TDC Duty Cycle (Measured at 100 MHz)
47 50 53 % 3
Jphase
THF-RMS
RMS phase jitter from 12kHz - 20MHz
>1.5MHz - 50MHz RMS jitter applying PCIE G2 jitter mask
0.4
2.2
1
3.1
ps
2
3
PSR
Power Supply Rejection with -30dBm input sine wave 100kHz
to 600kHz
-46
dBc 2
TEN/DIS
TLOCK
Output enable/disable time
PLL Lock Time
80 ns
5 ms
Notes:
1. Test configuration is RS = 33Ω, Rp = 49.9Ω with 2pF load.
2. Measurement taken from Single Ended waveform.
3. Measurement taken from Differential waveform.
12-0238
5
PI6LC4830 Rev B
08/17/12
5 Page Packaging Mechanical: 32-Pin TQFN (ZH)
PI6LC4830
HiFlexTM Network Clock Generator
Notes:
1. All dimensions are in mm. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals.
3. Refer JEDEC MO-220
4. Recommended land pattern is for reference only.
5. Thermal pad soldering area (mesh stencile design is recommended)
DESCRIPTION: 32-contact, Thin Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZH32
DOCUMENT CONTROL #: PD-2070
11-0147
Note:
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information(1-3)
Ordering Code
PI6LC4830ZHE
Package Code
ZH
Package Description
32-Pin, Pb-free & Green (TQFN)
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. Adding an X suffix = Tape/Reel
DATE: 06/30/11
REVISION: B
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
12-0238
All trademarks are property of their respective owners.
11
PI6LC4830 Rev B
08/17/12
11 Page |
Páginas | Total 11 Páginas | |
PDF Descargar | [ Datasheet PI6LC4830.PDF ] |
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