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PDF PI6LC48H02 Data sheet ( Hoja de datos )

Número de pieza PI6LC48H02
Descripción 3.0/2.0/1.0 Clock Generator
Fabricantes Pericom Semiconductor 
Logotipo Pericom Semiconductor Logotipo



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No Preview Available ! PI6LC48H02 Hoja de datos, Descripción, Manual

PI6LC48H02
PCIe® 3.0/2.0/1.0 Clock Generator with 2 HCSL Outputs
Features
ÎÎPCIe® 3.0/2.0/1.0 compliant
àà PCIe 3.0 Phase jitter - 0.45ps RMS (High Freq. Typ.)
ÎÎLVDS compatible outputs
ÎÎSupply voltage of 3.3V ±10%
ÎÎ25MHz crystal or clock input frequency
ÎÎHCSL outputs, 0.8V Current mode differential pair
ÎÎJitter 35ps cycle-to-cycle (typ)
ÎÎRMS phase jitter 12kHz ~ 20MHz @ 100MHz - 0.32ps (typ)
ÎÎRMS phase jitter 12kHz ~ 20MHz @ 125MHz - 0.3ps (typ)
ÎÎIndustrial temperature range
ÎÎPackaging: (Pb-free and Green)
àà 16-pin TSSOP (L16)
Description
The PI6LC48H02 is a clock generator compliant to PCI Express®
3.0/2.0/1.0 and Ethernet requirements. The device is used for PC
or embedded systems.
The PI6LC48H02 provides two differential (HCSL) or LVDS out-
puts. Using Pericom's patented Phase Locked Loop (PLL) tech-
niques, the device takes a 25MHz crystal input and produces
two pairs of differential outputs (HCSL) at 25MHz, 100MHz,
125MHz, 200MHz clock frequencies.
Block Diagram
Pin Configuration (16-Pin TSSOP)
VDD
S1:S0
2
X1/CLK
25 MHz
crystal or clock X2
Pulling
Capacitors
Control
Logic
Crystal
Driver
Phase
Lock
Loop
GND
RR
OE
CLK0
CLK0
CLK1
CLK1
S0
S1
NC
X1/CLK
X2
OE
GND
NC
1
2
3
4
5
6
7
8
16 VDDX
15 CLK0
14 CLK0
13 GNDA
12 VDDA
11 CLK1
10 CLK1
9 IREF
All trademarks are property of their respective owners.
14-0044
1 www.pericom.com PI6LC48H02 Rev.C
04/07/2014

1 page




PI6LC48H02 pdf
PI6LC48H02
PCIe® 3.0/2.0/1.0 Clock Generator with 2 HCSL Outputs
Application Information
LVDS Recommendations for Differential Routing
L1 length, route as non-coupled 50Ω trace.
L2 length, route as non-coupled 50Ω trace.
RP
RQ
RT
L3 length, route as 100Ω differential trace.
L3 length, route as 100Ω differential trace.
Dimension or Value
0.5 max
0.2 max
100
100
150
Unit
inch
inch
LVDS Device Routing
PI6LC48H02
Clock
Output
L1
RQ
L1’
RT
RT
L2’ L2
L3
L3’
RP
LVDS
Device
Load
All trademarks are property of their respective owners.
14-0044
5 www.pericom.com PI6LC48H02 Rev.C
04/07/2014

5 Page










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