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PDF PI6LC48L0201A Data sheet ( Hoja de datos )
| Número de pieza | PI6LC48L0201A | |
| Descripción | 2-Output LVDS Networking Clock Generator | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6LC48L0201A
2-Output LVDS Networking Clock Generator
Features
ÎÎTwo differential LVDS output pairs
ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL
single-ended clock input
ÎÎSupports the following output frequencies: 62.5MHz,
125MHz, 156.25MHz
ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.3ps (typical)
ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.5ps (max)
ÎÎFull 3.3V or 2.5V supply modes
ÎÎIndustrial operating temperature
ÎÎAvailable in lead-free package: 20-TQFN
Description
The PI6LC48L0201A is a 2-output LVDS synthesizer opti-
mized to generate Ethernet reference clock frequencies and is a
member of Pericom’s HiFlex family of high performance clock
solutions. Using a 25MHz crystal, the most popular Ethernet
frequencies can be generated based on the settings of 2 frequen-
cy select pins.
The PI6LC48L0201A uses Pericom’s proprietary low phase noise
PLL technology to achieve ultra low phase jitter, so it is ideal for
Ethernet interface in all kind of systems.
Applications
ÎÎNetworking systems
Block Diagram
XTAL_IN
XTAL_OUT
Ref_IN
IN_SEL
OSC
M_reset
PFD VCO
M
PLL_ByPass
N_SEL[0:1]
/N
CLK0
CLK0#
CLK1
CLK1#
15-0104
1 www.pericom.com PI6LC48L0201A
Rev. A
08/04/2015
1 page  
PI6LC48L0201A
2-Output LVDS Networking Clock Generator
LVDS DC Characterisitcs, (TA = -40ºC to 85ºC)
Symbol Parameter
VOD Differential Output Voltage
DVOD
Change of VOD
VOS Output Offset Voltage
DVOS
Change of VOS
Condition
VDD = 3.3V
VDD = 2.5V
VDD = 3.5V
VDD = 2.5V
VDD = 3.3V
VDD = 2.5V
VDD = 3.5V
VDD = 2.5V
Min Typ Max Units
247
247
454
454
mV
50
50
mV
1.125
1.125
1.375
1.375
V
50
50
mV
AC Electrical Characteristics, (TA = -40ºC to 85ºC)
Symbol Parameter
fOUT
tsk(o)
Output Frequency
Output Skew(1, 3)
tjit(Ø)
RMS Phase Jitter,
(Random)(2)
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
Condition
N_SEL[1:0] = 00
N_SEL[1:0] = 01
N_SEL[1:0] = 10
Outputs @ same loading
156.25MHz,
(1.875MHz - 20MHz)
156.25MHz,
(12kHz - 20MHz)
125MHz,
(1.875MHz - 20MHz)
125MHz,
(12kHz - 20MHz)
62.5MHz,
(1.875MHz - 20MHz)
62.5MHz,
(12kHz - 20MHz)
20% to 80%
Min.
140
112
56
48
Typ.
50
0.15
0.3
0.15
0.3
0.32
0.4
Max
170
136
68
0.3
0.5
0.3
0.5
0.5
0.7
400
52
Note:
1. Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.
2. Please refer to the Phase Noise Plots.
3. This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
%
15-0104
5 www.pericom.com PI6LC48L0201A
Rev. A
08/04/2015
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet PI6LC48L0201A.PDF ] | |
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