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PDF PI6LC48P25104 Data sheet ( Hoja de datos )
| Número de pieza | PI6LC48P25104 | |
| Descripción | Single Output LVPECL Clock Generator | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6LC48P25104
Single Output LVPECL Clock Generator
Features
ÎÎSingle differential LVPECL output
ÎÎOutput frequency range: 145MHz to 187.5MHz
ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.3ps (typical)
ÎÎFull 3.3V or 2.5V supply modes
ÎÎCommercial and industrial operating temperature
ÎÎAvailable in lead-free package: 8-TSSOP
Applications
ÎÎNetworking systems
ÎÎServers and Storage systems
Description
The PI6LC48P25104 is a single output LVPECL synthesizer
optimized to generate Ethernet reference clock frequencies and
is a member of Pericom’s HiFlex family of high performance
clock solutions. Using a 25MHz, it can generate 156.25MHz, or
187.5MHz output. Using other crystal frequencies, it can gener-
ate other popular frequencies for networking and server storage
systems.
The PI6LC48P25104 uses Pericom’s proprietary low phase noise
PLL technology to achieve ultra low phase jitter, so it is ideal for
SATA/SAS or Ethernet interface in all kind of systems.
Block Diagram
XTAL_IN
XTAL_OUT
OSC
PFD VCO
Freq_SEL
/M
/N
Pin Configuration
CLK VDDA 1
CLK#
GND 2
XTAL_OUT 3
XTAL_IN 4
8 VDD
7 CLK
6 CLK#
5 Freq_SEL
13-0109
1 www.pericom.com PI6LC48P25104
Rev. A
07/08/2013
1 page  
PI6LC48P25104
Single Output LVPECL Clock Generator
Power Supply Filtering Techniques
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The PI6LC48P25104 provides separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and
0.1μF bypass capacitors should be used for each pin. Figure below illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10Ω resistor along with a 10μF bypass capacitor be connected to the VDDA pin.
Crystal Input Interface
The clock generator has been characterized with 18pF parallel resonant crystals. The capacitor values shown in the figure below
were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
13-0109
5 www.pericom.com PI6LC48P25104
Rev. A
07/08/2013
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PI6LC48P25104.PDF ] | |
Hoja de datos destacado
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