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PDF MB9BF568F Data sheet ( Hoja de datos )
| Número de pieza | MB9BF568F | |
| Descripción | Microcontroller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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MB9B560R Series
32-Bit ARM® Cortex® - M4F
FM4 Microcontroller
Devices in the MB9B560R Series are highly integrated 32-bit microcontrollers with high performance and competitive cost.
This series is based on the ARM® Cortex®-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral
functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, CAN, UART, CSIO, I2C, LIN).
Features
32-bit ARM® Cortex®-M4F Core
Processor version: r0p1
Up to 160 MHz Frequency Operation
FPU built-in
Support DSP instruction
Memory Protection Unit (MPU): improves the reliability of an
embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
Flash memory
These series are based on two independent on-chip Flash
memories.
MainFlash memory
• Up to 1024 Kbytes
• Built-in Flash Accelerator System with 16 Kbytes trace
buffer memory
• The read access to Flash memory can be achieved
without wait-cycle up to operation frequency of 72 MHz.
Even at the operation frequency more than 72 MHz, an
equivalent access to Flash memory can be obtained by
Flash Accelerator System.
• Security function for code protection
WorkFlash memory
• 32 Kbytes
• Read cycle:
• 6wait-cycle: the operation frequency more than 120 MHz,
and up to 160 MHz
• 4wait-cycle: the operation frequency more than 72 MHz,
and up to 120 MHz
• 2wait-cycle: the operation frequency more than 40 MHz,
and up to 72 MHz
• 0wait-cycle: the operation frequency up to 40 MHz
• Security function is shared with code protection
SRAM
This is composed of three independent SRAMs (SRAM0,
SRAM1, and SRAM2). SRAM0 is connected to I-code bus and
D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are
connected to System bus of Cortex-M4F core.
SRAM0: Up to 64 Kbytes
SRAM1: Up to 32 Kbytes
SRAM2: Up to 32 Kbytes
External Bus Interface
Supports SRAM, NOR, NAND Flash, and SDRAM device
Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
8-/16-bit Data width
Up to 25-bit Address bit
Supports Address/Data multiplex
Supports external RDY function
Supports scramble function
Possible to set the validity/invalidity of the scramble
function for the external areas 0x6000_0000 to
0xDFFF_FFFF in 4 Mbytes units.
Possible to set two kinds of the scramble key
Note:
• It is necessary to prepare the dedicated software library
to use the scramble function.
USB Interface
USB interface is composed of Function and Host.
[USB function]
USB2.0 Full-Speed supported
Max 6 Endpoint supported
Endpoint 0 is control transfer
Endpoint 1, 2 can be selected Bulk-transfer,
Interrupt-transfer or Isochronous-transfer
Endpoint 3 to 5 can select Bulk-transfer or
Interrupt-transfer
Endpoint 1 to 5 comprise Double Buffer
The size of each endpoint is according to the follows.
• Endpoint 0, 2 to 5: 64 bytes
• Endpoint 1: 256 bytes
Cypress Semiconductor Corporation
Document Number: 002-04864 Rev.*A
• 198 Champion Court • San Jose, CA 95134-1709
408-943-2600
Revised March 3, 2016
1 page  
MB9B560R Series
Contents
1. Product Lineup.................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment ................................................................................................................................................................. 9
4. Pin Description................................................................................................................................................................ 15
4.1 List of Pin Numbers ..................................................................................................................................................... 15
4.2 List of Pin Functions .................................................................................................................................................... 28
5. I/O Circuit Type ............................................................................................................................................................... 44
6. Handling Precautions ..................................................................................................................................................... 51
6.1 Precautions for Product Design................................................................................................................................... 51
6.2 Precautions for Package Mounting.............................................................................................................................. 52
6.3 Precautions for Use Environment ................................................................................................................................ 53
7. Handling Devices ............................................................................................................................................................ 54
8. Block Diagram ................................................................................................................................................................. 57
9. Memory Size .................................................................................................................................................................... 58
10. Memory Map .................................................................................................................................................................... 58
11. Pin Status in Each CPU State ........................................................................................................................................ 61
12. Electrical Characteristics ............................................................................................................................................... 69
12.1 Absolute Maximum Ratings......................................................................................................................................... 69
12.2 Recommended Operating Conditions ......................................................................................................................... 70
12.3 DC Characteristics ...................................................................................................................................................... 74
12.3.1 Current Rating.............................................................................................................................................................. 74
12.3.2 Pin Characteristics ....................................................................................................................................................... 81
12.4 AC Characteristics....................................................................................................................................................... 83
12.4.1 Main Clock Input Characteristics.................................................................................................................................. 83
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 84
12.4.3 Built-in CR Oscillation Characteristics.......................................................................................................................... 84
12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL)...................................... 85
12.4.5 Operating Conditions of USB PLL (In the Case of Using Main Clock for Input Clock of PLL) ...................................... 85
12.4.6 Operating Conditions of Main PLL (In the Case of Using Built-in High-speed CR Clock for
Input Clock of Main PLL).............................................................................................................................................. 85
12.4.7 Reset Input Characteristics .......................................................................................................................................... 86
12.4.8 Power-on Reset Timing................................................................................................................................................ 86
12.4.9 GPIO Output Characteristics........................................................................................................................................ 87
12.4.10 External Bus Timing ................................................................................................................................................. 87
12.4.11 Base Timer Input Timing......................................................................................................................................... 100
12.4.12 UART Timing .......................................................................................................................................................... 101
12.4.13 External Input Timing.............................................................................................................................................. 134
12.4.14 Quadrature Position/Revolution Counter Timing .................................................................................................... 135
12.4.15 I2C Timing............................................................................................................................................................... 137
12.4.16 SD Card Interface Timing ....................................................................................................................................... 139
12.4.17 ETM Timing ............................................................................................................................................................ 142
12.4.18 JTAG Timing........................................................................................................................................................... 143
12.5 12-bit A/D Converter.................................................................................................................................................. 144
12.6 12-bit D/A Converter.................................................................................................................................................. 147
12.7 USB Characteristics .................................................................................................................................................. 148
12.8 Low-Voltage Detection Characteristics...................................................................................................................... 152
Document Number: 002-04864 Rev.*A
Page 5 of 169
5 Page 
FPT-120P-M37
(TOP VIEW)
MB9B560R Series
VCC 1
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0 2
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0 3
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0 4
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0 5
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0 6
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 7
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 8
P57/SCK6_0/MADATA07_0 9
P58/SIN4_2/AIN1_0/INT04_2/MADATA08_0 10
P59/RX1_1/SOT4_2/BIN1_0/INT07_1/MADATA09_0 11
P5A/TX1_1/SCK4_2/ZIN1_0/MADATA10_0 12
P5B/CTS4_2/MADATA11_0 13
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA12_0 14
P31/TIOB1_1/SIN3_1/INT09_2/MADATA13_0 15
P32/TIOB2_1/SOT3_1/INT10_1/MADATA14_0 16
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA15_0 17
P34/TX0_1/TIOB4_1/FRCK0_0/MNALE_0 18
P35/RX0_1/TIOB5_1/IC03_0/INT08_1/MNCLE_0 19
P36/SIN5_2/IC02_0/INT09_1/MNWEX_0 20
P37/SOT5_2/IC01_0/INT05_2/MNREX_0 21
P38/SCK5_2/IC00_0/INT06_2 22
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0 23
P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0 24
P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0 25
P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0 26
P3D/TIOA3_1/RTO03_0/MAD00_0 27
P3E/TIOA4_1/RTO04_0/MAD01_0 28
P3F/TIOA5_1/RTO05_0/MAD02_0 29
VSS 30
LQFP - 120
90 VSS
89 P20/AN18/AIN1_1/INT05_0/MAD24_0
88 P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0
87 P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1
86 P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0
85 P24/RX1_0/SIN2_1/RTO01_1/INT01_2
84 P25/TX1_0/TIOA5_0/SOT2_1/RTO02_1
83 P26/TIOB5_0/SCK2_1/RTO03_1
82 P27/TIOA6_2/RTO04_1/INT02_2
81 P1F/ADTG_4/TIOB6_2/RTO05_1
80 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0
79 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0
78 P1C/AN12/CTS4_1/IC03_1/MAD19_0
77 P1B/AN11/SCK4_1/IC02_1/MAD18_0
76 P1A/AN10/SOT4_1/IC01_1/MAD17_0
75 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
74 P18/AN08/SCK2_2/MAD15_0
73 AVRH
72 AVRL
71 AVSS
70 AVCC
69 P17/AN07/SOT2_2/WKUP3/MAD14_0
68 P16/AN06/SIN2_2/INT14_1/MAD13_0
67 P15/AN05/SCK0_1/MAD12_0
66 P14/AN04/SOT0_1/IC03_2/MAD11_0
65 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
64 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
63 P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0
62 P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0
61 VCC
Note:
• The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04864 Rev.*A
Page 11 of 169
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MB9BF568F.PDF ] | |
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