WM5102S Datasheet PDF - Wolfson Microelectronics
| Part Number | WM5102S | |
| Description | Audio Hub CODEC | |
| Manufacturers | Wolfson Microelectronics | |
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WM5102S
Audio Hub CODEC with Master Hi-Fi DSP
DESCRIPTION
The WM5102S[1] is a highly-integrated low-power audio
system for smartphones, tablets and other portable audio
devices. It supports audiophile quality DAC playback on a
flexible, high-performance audio hub.
The WM5102S digital core provides a powerful combination
of fixed-function signal processing blocks with a
programmable DSP. These are supported by a fully-flexible,
all-digital audio mixing and routing engine with sample rate
converters, for wide use-case flexibility. The programmable
DSP supports a range of audio processing software
packages, including user-programmed solutions. A suite of
signal processing software packages is licensed as part of
the WM5102S product, though different audio algorithms
can also be implemented. Fixed-function signal processing
blocks include filters, EQ, dynamics processors and sample
rate converters.
A SLIMbus interface supports multi-channel audio paths and
host control register access. Multiple sample rates are
supported concurrently via the SLIMbus interface. Three
further digital audio interfaces are provided, each supporting
a wide range of standard audio sample rates and serial
interface formats. Automatic sample rate detection enables
seamless wideband/narrowband voice call handover.
Two stereo headphone drivers each provide stereo ground-
referenced or mono BTL outputs, with noise levels as low as
1µVRMS (HPOUT1) for hi-fi quality line or headphone output.
The CODEC also features stereo 2W Class-D speaker
outputs, a dedicated BTL earpiece output and PDM for
external speaker amplifiers. A signal generator for
controlling haptics devices is included; vibe actuators can
connect directly to the Class-D speaker output, or via an
external driver on the PDM output interface. All inputs,
outputs and system interfaces can function concurrently.
The WM5102S supports up to six microphone inputs, each
either analogue or PDM digital. Microphone activity
detection with interrupt is available. A smart accessory
interface supports most standard 3.5mm accessories.
Impedance sensing and measurement is provided for
external accessory and push-button detection.
The WM5102S power, clocking and output driver
architectures are all designed to maximise battery life in
voice, music and standby modes. Low-power ‘Sleep’ is
supported, with configurable wake-up events. The
WM5102S is powered from a 1.8V external supply. A
separate supply is required for the Class D speaker drivers
(typically direct connection to 4.2V battery).
Two integrated FLLs provide support for a wide range of
system clock frequencies. The WM5102S is configured using
the I2C, SPI or SLIMbus interfaces. The fully-differential
internal analogue architecture, minimal analogue signal
paths and on-chip RF noise filters ensure a very high degree
of noise immunity.
FEATURES
Audio hub CODEC with integrated DSP
Master Hi-Fi filters for audiophile quality DAC playback
Enhanced DRE processing (eDRE) for 120dB SNR
Fixed function signal processing functions
- Wind noise, sidetone and other high/low pass filters
- Dynamic Range Control, Fully parametric EQs
- Tone, Noise, PWM, Haptic control signal generators
Multi-channel asynchronous sample rate conversion
Integrated 6/7 channel 24-bit hi-fi audio hub CODEC
- 6 ADCs, 96dB SNR microphone input (48kHz)
- 7 DACs, 120dB SNR headphone playback (48kHz)
Audio inputs
- Up to 6 analogue or digital microphone inputs
- Single-ended or differential mic/line inputs
Multi-purpose headphone / earpiece / line output drivers
- 2 stereo output paths
- 29mW into 32Ω load at 0.1% THD+N
- 100mW into 32Ω BTL load at 5% THD+N
- 6.5mW typical headphone playback power consumption
- Pop suppression functions
- 1µVRMS noise floor (A-weighted, HPOUT1)
Mono BTL earpiece output driver
2 x 2W stereo Class D speaker output drivers
- Direct drive of external haptics vibe actuators
Two-channel digital speaker (PDM) interface
SLIMbus® audio and control interface
3 full digital audio interfaces
- Standard sample rates from 4kHz up to 192kHz
- Ultrasonic accessory function support
- TDM support on all AIFs
- 8 channel input and output on AIF1
Flexible clocking, derived from MCLKn, BCLKn or SLIMbus
2 low-power FLLs support reference clocks down to 32kHz
Advanced accessory detection functions
- Low-power standby mode and configurable wake-up
Configurable functions on 5 GPIO pins
Integrated LDO regulators and charge pumps
Support for single 1.8V supply operation
Small W-CSP package, 0.4mm pitch
APPLICATIONS
Smartphones and Multimedia handsets
Tablets and Mobile Internet Devices (MID)
Portable Music Players (PMP)
WOLFSON MICROELECTRONICS plc
Product Preview, April 2014, Rev 1.1
[1] This product is protected by Patents US 7,622,984, US 7,626,445, US 7,765,019 and GB 2,432,765
Copyright 2014 Wolfson Microelectronics plc
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Product Preview
WM5102S
EXTERNAL ACCESSORY DETECTION ................................................................................ 178
JACK DETECT ............................................................................................................................................................................178
JACK POP SUPPRESSION (MICDET CLAMP)..........................................................................................................................180
MICROPHONE DETECT.............................................................................................................................................................181
HEADPHONE DETECT...............................................................................................................................................................186
LOW POWER SLEEP CONFIGURATION .............................................................................. 190
SLEEP MODE..............................................................................................................................................................................190
SLEEP CONTROL SIGNALS - JD1, GP5, MICDET CLAMP ......................................................................................................193
WAKE-UP TRANSITION .............................................................................................................................................................195
WRITE SEQUENCE CONTROL..................................................................................................................................................196
INTERRUPT CONTROL..............................................................................................................................................................196
GENERAL PURPOSE INPUT / OUTPUT ............................................................................... 197
GPIO CONTROL .........................................................................................................................................................................198
GPIO FUNCTION SELECT .........................................................................................................................................................200
DIGITAL AUDIO INTERFACE FUNCTION (AIFNTXLRCLK) ......................................................................................................203
BUTTON DETECT (GPIO INPUT)...............................................................................................................................................204
LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT (GPIO OUTPUT) ................................................................................................................204
INTERRUPT (IRQ) STATUS OUTPUT........................................................................................................................................204
DSP STATUS FLAG (DSP IRQN) OUTPUT ...............................................................................................................................205
OPCLK AND OPCLK_ASYNC CLOCK OUTPUT .......................................................................................................................205
FREQUENCY LOCKED LOOP (FLL) STATUS OUTPUT ...........................................................................................................206
FREQUENCY LOCKED LOOP (FLL) CLOCK OUTPUT .............................................................................................................207
PULSE WIDTH MODULATION (PWM) SIGNAL OUTPUT .........................................................................................................207
HEADPHONE DETECTION STATUS OUTPUT .........................................................................................................................208
MICROPHONE / ACCESSORY DETECTION STATUS OUTPUT ..............................................................................................208
ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) LOCK STATUS OUTPUT .............................................................208
ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) CONFIGURATION ERROR STATUS OUTPUT ...........................209
OVER-TEMPERATURE STATUS OUTPUT ...............................................................................................................................209
DYNAMIC RANGE CONTROL (DRC) STATUS OUTPUT ..........................................................................................................209
CONTROL WRITE SEQUENCER STATUS OUTPUT ................................................................................................................210
CONTROL INTERFACE ERROR STATUS OUTPUT .................................................................................................................210
SYSTEM CLOCKS ENABLE STATUS OUTPUT ........................................................................................................................210
CLOCKING ERROR STATUS OUTPUT .....................................................................................................................................211
DIGITAL AUDIO INTERFACE CONFIGURATION ERROR STATUS OUTPUT .........................................................................212
INTERRUPTS .......................................................................................................................... 213
CLOCKING AND SAMPLE RATES ......................................................................................... 225
SYSTEM CLOCKING ..................................................................................................................................................................225
SAMPLE RATE CONTROL .........................................................................................................................................................225
AUTOMATIC SAMPLE RATE DETECTION................................................................................................................................226
SYSCLK AND ASYNCCLK CONTROL .......................................................................................................................................227
MISCELLANEOUS CLOCK CONTROLS ....................................................................................................................................230
BCLK AND LRCLK CONTROL....................................................................................................................................................237
CONTROL INTERFACE CLOCKING ..........................................................................................................................................237
FREQUENCY LOCKED LOOP (FLL) ..........................................................................................................................................238
FREE-RUNNING FLL MODE ......................................................................................................................................................248
SPREAD SPECTRUM FLL CONTROL .......................................................................................................................................249
GPIO OUTPUTS FROM FLL .......................................................................................................................................................250
EXAMPLE FLL CALCULATION...................................................................................................................................................250
EXAMPLE FLL SETTINGS..........................................................................................................................................................251
CONTROL INTERFACE .......................................................................................................... 252
2-WIRE (I2C) CONTROL MODE .................................................................................................................................................253
4-WIRE (SPI) CONTROL MODE.................................................................................................................................................257
CONTROL WRITE SEQUENCER ........................................................................................... 258
INITIATING A SEQUENCE..........................................................................................................................................................258
AUTOMATIC SAMPLE RATE DETECTION SEQUENCES ........................................................................................................259
JACK DETECT, GPIO, MICDET CLAMP, AND WAKE-UP SEQUENCES .................................................................................260
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PP, April 2014, Rev 1.1
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for WM5102S electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ WM5102S.PDF Datasheet ] | |
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