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PDF TB67S215FTAG Data sheet ( Hoja de datos )
| Número de pieza | TB67S215FTAG | |
| Descripción | PWM method CLOCK-IN Bipolar stepping motor driver | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TOSHIBA BiCD Integrated Circuit Silicon Monolithic
TB67S215FTAG
TB67S215FTAG
PWM method CLOCK-IN Bipolar stepping motor driver
The TB67S215FTAG is a pwm method clock-in controlled
motor driver for two-phase bipolar stepping motor.
Using the BiCD process, the TB67S215FTAG is rated at
40V/2.5A.(Absolute maximum ratings)
Also, with the built-in VCC regulator, the TB67S215FTAG
can be operated with a single motor power(VM) supply.
Features
P-WQFN36-0606-0.50－002
Weight:0.14(g)
・The TB67S215FTAG can operate a single bipolar stepping motor.
・PWM method current feedback control.
・Operational in Full, Half, and Quarter step resolutions.
・Uses low on-resistance MOSFETs for output stage.
・High voltage and large current. (For specification, please refer to the absolute maximum ratings
and operation ranges.)
・Error detection circuits (Thermal Shutdown(TSD), Over current shutdown(ISD), and Power-on reset(POR))
・The built-in VCC regulator allows the TB67S215FTAG to operate with a single VM power supply.
・Customizable PWM chopping frequency using the external components (resistance/capacitor).
・Package: P-WQFN36-0606-0.50-002
Note) Please be careful about thermal conditions during use.
1 2013-08-19
Ver.1.02
1 page  
Equivalent circuit
TB67S215FTAG(QFN36)
1,2,3,33,35,36
1kΩ
GND
25
30,31
1kΩ
TB67S215FTAG
6,7
21,22
8,9
19,20
GND
1kΩ
32
11,12
16,17
34
GND
GND
GND
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.
Pin No
1
2
3
6,7
8,9
11,12
16,17
19,20
21,22
23
25
30
31
32
33
34
35
36
Pin name
CLK_IN
ENABLE
RESET
RS_A
OUT_A+
OUT_A－
OUT_B－
OUT_B＋
RS_B
VM
VCC
VREF_B
VREF_A
OSCM
CW/CCW
MO_OUT
D_MODE1
D_MODE2
5 2013-08-19
Ver.1.02
5 Page 
TB67S215FTAG
Electrical Specifications 2 (Ta = 25°C, VM = 24 V, 6.8 mH/5.7 Ω)
Characteristics
CLK input frequency
Minimum CLK High width
Minimum CLK Low width
Output stage
Switching specifications
Analog noise rejection blank time
Internal oscillator frequency
Motor chopping frequency
Symbol
fCLK
Test
Circuit
AC
Test Condition
fOSC=1600kHz
Min Typ. Max
- - 100
tCLK(H) AC Minimum CLK width: CLK=‘H’ 300 -
-
tCLK(L)
tr
tf
tpLH(CLK)
tpHL(CLK)
AtBLK
fOSC
fchop
AC Minimum CLK width: CLK=‘L’ 250
AC 100
AC 100
AC CLK to OUT
-
AC CLK to OUT
-
VM=24V,IOUT=1.0A
AC 250
Analog tBLK
AC COSC= 270 pF, ROSC =3.6 kΩ 1360
AC
Output active (IOUT =1.0 A),
fOSC = 1600 kHz
-
-
150
150
1000
1500
-
200
200
-
-
400 550
1600 1840
100 -
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
kHz
kHz
AC timing chart
1/fCLK
【CLK】
50%
tCLK(H)
tCLK(L)
50%
50%
【OUT】
tpLH(CLK)
50%
90%
10%
tr
tpHL(CLK)
90%
50%
10%
tf
Timing charts may be simplified for explanatory purpose.
11 2013-08-19
Ver.1.02
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet TB67S215FTAG.PDF ] | |
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