PDF MK64FX512VLL12 Data sheet ( Hoja de datos )

Número de pieza	MK64FX512VLL12
Descripción	Microcontroller
Fabricantes	Freescale Semiconductor
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No Preview Available ! NXP Semiconductors Data Sheet: Technical Data K64P144M120SF5 Rev. 7, 10/2016 Kinetis K64F Sub-Family Data Sheet 120 MHz ARM® Cortex®-M4-based Microcontroller with FPU The K64 product family members are optimized for cost-sensitive applications requiring low-power, USB/Ethernet connectivity, and up to 256 KB of embedded SRAM. These devices share the comprehensive enablement and scalability of the Kinetis family. This product offers: • Run power consumption down to 250 μA/MHz. Static power consumption down to 5.8 μA with full state retention and 5 μs wakeup. Lowest Static mode down to 339 nA • USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO Vreg, with USB device crystal-less operation • 10/100 Mbit/s Ethernet MAC with MII and RMII interfaces MK64FN1M0Vxx12 MK64FX512Vxx12 121 XFBGA 144 LQFP 8 x 8 x 0.5 mm Pitch 20 x 20 x 1.6 mm Pitch 0.65 mm 0.5 mm 144 MAPBGA 13 x 13 x 1.46 mm Pitch 1 mm 100 QFP 14 x 14 x 1.7 mm Pitch 0.5 mm Performance • Up to 120 MHz ARM® Cortex®-M4 core with DSP instructions and floating point unit Memories and memory interfaces • Up to 1 MB program flash memory and 256 KB RAM • Upto 128 KB FlexNVM and 4 KB FlexRAM on devices with FlexMemory • FlexBus external bus interface Communication interfaces • Ethernet controller with MII and RMII interface • USB full-/low-speed On-the-Go controller • Controller Area Network (CAN) module • Three SPI modules • Three I2C modules. Support for up to 1 Mbit/s • Six UART modules • Secure Digital Host Controller (SDHC) • I2S module System peripherals • Multiple low-power modes, low-leakage wake-up unit • Memory protection unit with multi-master protection • 16-channel DMA controller • External watchdog monitor and software watchdog Security and integrity modules • Hardware CRC module • Hardware random-number generator • Hardware encryption supporting DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms • 128-bit unique identification (ID) number per chip Timers • Two 8-channel Flex-Timers (PWM/Motor control) • Two 2-channel FlexTimers (PWM/Quad decoder) • IEEE 1588 timers • 32-bit PITs and 16-bit low-power timers • Real-time clock • Programmable delay block Clocks • 3 to 32 MHz and 32 kHz crystal oscillator • PLL, FLL, and multiple internal oscillators • 48 MHz Internal Reference Clock (IRC48M) Analog modules • Two 16-bit SAR ADCs • Two 12-bit DACs • Three analog comparators (CMP) • Voltage reference Operating Characteristics • Voltage range: 1.71 to 3.6 V • Flash write voltage range: 1.71 to 3.6 V • Temperature range (ambient): –40 to 105°C NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. 1 page Ratings 1 Ratings 1.1 Thermal handling ratings Symbol TSTG TSDR Description Storage temperature Solder temperature, lead-free Solder temperature, leaded Min. –55 — — Max. 150 260 245 Unit Notes °C 1 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Symbol Description MSL Moisture sensitivity level Min. — Max. 3 Unit Notes —1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Symbol VHBM VCDM ILAT Description Electrostatic discharge voltage, human body model Electrostatic discharge voltage, charged-device model Latch-up current at ambient temperature of 105°C Min. -2000 -500 -100 Max. +2000 +500 +100 Unit V V mA Notes 1 2 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 1.4 Voltage and current operating ratings Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 5 NXP Semiconductors 5 Page General 2.2.5 Power consumption operating behaviors NOTE The maximum values represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 6. Power consumption operating behaviors Symbol Description IDDA IDD_RUN Analog supply current Run mode current — all peripheral clocks disabled, code executing from flash • @ 1.8V • @ 3.0V Min. — Typ. — Max. See note — 31.1 36.65 — 31 36.75 IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash • @ 1.8V • @ 3.0V • @ 25°C • @ 105°C — 42.7 48.35 — 40 41.60 — 48.33 51.50 IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled IDD_VLPW Very-low-power wait mode current at 3.0 V — all peripheral clocks disabled IDD_STOP Stop mode current at 3.0 V • @ –40 to 25°C • @ 70°C • @ 105°C — — — — — — — — 17.9 6.9 1.0 1.7 0.678 — — — — — 0.49 1.24 1.18 4.3 3.0 12.5 IDD_VLPS Very-low-power stop mode current at 3.0 V • @ –40 to 25°C • @ 70°C • @ 105°C — 57 139.31 — 291 679.33 — 927.3 1869.85 IDD_LLS Low leakage stop mode current at 3.0 V Table continues on the next page... Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA μA μA μA Notes 1 2 3, 4 2 5 6 7 8 9 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 11 NXP Semiconductors 11 Page

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