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PDF DVGA2-33PP Data sheet ( Hoja de datos )
| Número de pieza | DVGA2-33PP | |
| Descripción | Digital Controlled Variable Gain Amplifier | |
| Fabricantes | Mini-Circuits | |
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Digital Controlled Variable Gain Amplifier
50Ω 0.05 to 3 GHz
31.5 dB, 0.5 dB Step, 6 Bit Parallel Control
The Big Deal
• Integrated Amplifier and Digital Attenuator
• 19 dB Gain / 31.5 dB Gain Control
• Flat frequency response, ±0.7 dB (700-2100 MHz)
DVGA2-33PP+
CASE STYLE: DG1677
Product Overview
The DVGA2-33PP+ is a 50W RF Digital Variable Gain Amplifier that offers an attenuation of 31.5 dB in
0.5 dB steps using a 6-bit Parallel interface attenuator and 19dB gain using a InGap HBT amplifier. Step
attenuator used in DVGA2-33PP+ is produced using a unique combination of CMOS process on silicon,
offering the performance of GaAs, with the advantages of conventional CMOS devices.
Key Features
Feature
31.5 dB attenuation in 0.5 dB step size
Flat frequency response, ±0.7 over
700-2100 MHz
Medium Gain, 19 dB
Advantages
Combining medium gain and a wide range of gain control makes the DVGA2-
33PP+ an ideal building block for any RF chain where level setting control is
required in a fast speed of parallel control interface.
No need for external components to flatten gain.
Incorporating multiple stages of amplification, the DVGA2-33PP+ provides medium
gain over a wideband reducing cost and PCB board space.
Good IP3, +30 dBm at 1.0 GHz
Use in receivers and transmitters giving the users advantage in instantenous spur
free dynamic range over wide bandwidths.
Output Power, +16.3 dBm at 1.0 GHz
The DVGA2-33PP+ maintains consistent output power capability over the full
attenuation range and operating temperature range making it ideal to be used in
remote applications such as LNB’s as the L Band driver stage.
Attenuation Step size, 0.5 dB, accuracy
0.1 to 0.5 dB typ. Total attenuation, 31.5 dB
Enables precise control of gain in 0.5 dB steps up to 31.5 dB.
MCLP Package
Low Inductance, repeatable transitions, excellent thermal pad.
PCB area reduction
The DVGA2-33PP+ combines multiple functions common to TX/RX architectures
into a single 5x5mm package
Flexibility in the application block diagram
The DVGA2-33PP+ provides access to the internal circuit through external jumper
(see simplified schematic) enables designers flexibility to incorporate a wide range
of additional circuits.
Notes
A. Performance and quality attributes and conditions not expressly stated in this specification document are intended to be excluded and do not form a part of this specification document.
B. Electrical specifications and performance data contained in this specification document are based on Mini-Circuit’s applicable established test performance criteria and measurement instructions.
C. The parts covered by this specification document are subject to Mini-Circuits standard limited warranty and terms and conditions (collectively, “Standard Terms”); Purchasers of this part are entitled
to the rights and benefits contained therein. For a full statement of the Standard Terms and the exclusive rights and remedies thereunder, please visit Mini-Circuits’ website at www.minicircuits.com/MCLStore/terms.jsp
Mini-Circuits®
www.minicircuits.com P.O. Box 350166, Brooklyn, NY 11235-0003 (718) 934-4500 [email protected]
Page 1
1 page  
Digital Controlled Variable Gain Amplifier (DVGA)
DVGA2-33PP+
Table 1. Pad Description
Pin
Number
1
Function
N/C
2 RF IN
3 N/C
4 N/C
5 N/C
6 GND
7 LE
8 VD1
9 PUP1
10 PUP2
11 VD1
12 GND
13 GND
14 N/C
15 N/C
16 N/C
17 RF OUT &VD2
Description
Not Connected
RF Input Port (Note 1)
Not Connected
Not Connected
Not Connected (Note 4)
Ground
Latch Enable Input (Note 2)
VD1 Power Supply Input (Note 6)
Power-Up Selection
Power-Up Selection
VD1 Power Supply Input
Ground
Ground
Not Connected
Not Connected
Not Connected
RF output and VD2 on same pad
(external Bias Tee) (Note1,6)
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PADDLE
N/C
N/C
N/C
N/C
RF JUMP IN
RF JUMP OUT
N/C
N/C
C8
C4
C2
C1
C0.5
C16
N/C
GND
Not Connected
Not Connected
Not Connected
Not Connected
Interstage RF Jumper Input (Note 1)
Interstage RF Jumper Output (Note 1)
Not Connected
Not Connected
Power Up Control for 8dB Att. Bit (Note 4)
Power Up Control for 4dB Att. Bit (Note 4)
Power Up Control for 2dB Att. Bit (Note 4)
Power Up Control for 1dB Att. Bit (Note 4)
Power Up Control for 0.5dB Att. Bit (Note 4)
Power Up Control for 16dB Att. Bit (Note 3,4)
Not Connected
Ground (Note5)
N/C
RFin
N/C
N/C
N/C
GND
LE
VD1
1
2
3
4
5
6
7
8
Paddle
Ground
Notes:
1. All RF input and output ports shall be AC coupled with external blocking capacitor.
2. Latch Enable (LE) has an internal 100KW pull-up resistor to VD1
3. Place a 10KW resistor in series, as close to pin as possible to avoid freq. resonance (see layout drawing PL-TBD).
4. Place a 10KW resistor to ground.
5. The exposed solder pad on the bottom of the package (See Pin Configuration) must be grounded for proper device operation
6. See application and characterization test circuit and layout drawing PL-TBD.
24 N/C
23 RF jump out
22 RF jump in
21 N/C
20 N/C
19 N/C
18 N/C
17 RFout and VD2
Notes
A. Performance and quality attributes and conditions not expressly stated in this specification document are intended to be excluded and do not form a part of this specification document.
B. Electrical specifications and performance data contained in this specification document are based on Mini-Circuit’s applicable established test performance criteria and measurement instructions.
C. The parts covered by this specification document are subject to Mini-Circuits standard limited warranty and terms and conditions (collectively, “Standard Terms”); Purchasers of this part are entitled
to the rights and benefits contained therein. For a full statement of the Standard Terms and the exclusive rights and remedies thereunder, please visit Mini-Circuits’ website at www.minicircuits.com/MCLStore/terms.jsp
Mini-Circuits®
www.minicircuits.com P.O. Box 350166, Brooklyn, NY 11235-0003 (718) 934-4500 [email protected]
Page 5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet DVGA2-33PP.PDF ] | |
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