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PDF LM3S2410 Data sheet ( Hoja de datos )
| Número de pieza | LM3S2410 | |
| Descripción | Microcontroller | |
| Fabricantes | Luminary | |
| Logotipo |  |
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PRELIMINARY
LM3S2410 Microcontroller
DATA SHEET
DS-LM3S2410-03
Copyright © 2007 Luminary Micro, Inc.
1 page  
LM3S2410 Microcontroller
10.5 Register Descriptions .............................................................................................................. 198
11
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.2.7
11.2.8
11.3
11.4
11.5
UART ................................................................................................................................. 219
Block Diagram ........................................................................................................................ 220
Functional Description ............................................................................................................. 220
Transmit/Receive Logic ........................................................................................................... 220
Baud-Rate Generation ............................................................................................................. 221
Data Transmission .................................................................................................................. 222
Serial IR (SIR) ......................................................................................................................... 222
FIFO Operation ....................................................................................................................... 223
Interrupts ................................................................................................................................ 223
Loopback Operation ................................................................................................................ 224
IrDA SIR block ........................................................................................................................ 224
Initialization and Configuration ................................................................................................. 224
Register Map .......................................................................................................................... 225
Register Descriptions .............................................................................................................. 226
12 SSI ..................................................................................................................................... 259
12.1 Block Diagram ........................................................................................................................ 259
12.2 Functional Description ............................................................................................................. 259
12.2.1 Bit Rate Generation ................................................................................................................. 260
12.2.2 FIFO Operation ....................................................................................................................... 260
12.2.3 Interrupts ................................................................................................................................ 260
12.2.4 Frame Formats ....................................................................................................................... 261
12.3 Initialization and Configuration ................................................................................................. 268
12.4 Register Map .......................................................................................................................... 269
12.5 Register Descriptions .............................................................................................................. 270
13 CAN ................................................................................................................................... 293
13.1 Controller Area Network Overview ............................................................................................ 293
13.2 Controller Area Network Features ............................................................................................ 293
13.3 Controller Area Network Block Diagram .................................................................................... 294
13.4 Controller Area Network Functional Description ......................................................................... 295
13.4.1 Initialization ............................................................................................................................. 295
13.4.2 Operation ............................................................................................................................... 296
13.4.3 Transmitting Message Objects ................................................................................................. 296
13.4.4 Configuring a Transmit Message Object .................................................................................... 296
13.4.5 Updating a Transmit Message Object ....................................................................................... 297
13.4.6 Accepting Received Message Objects ...................................................................................... 297
13.4.7 Receiving a Data Frame .......................................................................................................... 298
13.4.8 Receiving a Remote Frame ...................................................................................................... 298
13.4.9 Receive/Transmit Priority ......................................................................................................... 298
13.4.10 Configuring a Receive Message Object .................................................................................... 298
13.4.11 Handling of Received Message Objects .................................................................................... 299
13.4.12 Handling of Interrupts .............................................................................................................. 299
13.4.13 Bit Timing Configuration Error Considerations ........................................................................... 300
13.4.14 Bit Time and Bit Rate ............................................................................................................... 300
13.4.15 Calculating the Bit Timing Parameters ...................................................................................... 302
13.5 Controller Area Network Register Map ...................................................................................... 304
13.6 Register Descriptions .............................................................................................................. 306
June 26, 2007
Preliminary
5
5 Page 
LM3S2410 Microcontroller
List of Registers
System Control .............................................................................................................................. 50
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 58
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 60
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 61
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 62
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 63
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 64
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 65
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 66
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 69
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 70
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 72
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 73
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 75
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 76
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 78
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 79
Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 80
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 81
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 82
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 83
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 84
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 86
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ......................... 88
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 .................................... 90
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 .................................. 92
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ......................... 94
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................... 96
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................... 97
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................... 98
Internal Memory ............................................................................................................................. 99
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 104
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 105
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 106
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 108
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 109
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 110
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 111
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 112
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 113
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 114
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 115
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 116
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 117
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 118
June 26, 2007
Preliminary
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LM3S2410.PDF ] | |
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