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PDF AD6672 Data sheet ( Hoja de datos )
| Número de pieza | AD6672 | |
| Descripción | IF Receiver | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
11-bit, 250 MSPS output data rate
Performance with NSR enabled
SNR: 75.2 dBFS in a 55 MHz band to 185 MHz at 250 MSPS
SNR: 72.8 dBFS in an 82 MHz band to 185 MHz at 250 MSPS
Performance with NSR disabled
SNR: 66.4 dBFS up to 185 MHz at 250 MSPS
SFDR: 87 dBc up to 185 MHz at 250 MSPS
Total power consumption: 358 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
Serial port control
Energy saving power-down modes
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA
I/Q demodulation systems
General-purpose software radios
IF Receiver
AD6672
GENERAL DESCRIPTION
The AD6672 is an 11-bit intermediate receiver with sampling
speeds of up to 250 MSPS. The AD6672 is designed to support
communications applications, where low cost, small size, wide
bandwidth, and versatility are desired.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer is provided
to compensate for variations in the ADC clock duty cycle,
allowing the converters to maintain excellent performance.
The ADC core output is connected internally to a noise shaping
requantizer (NSR) block. The device supports two output modes
that are selectable via the serial port interface (SPI). With the
NSR feature enabled, the outputs of the ADCs are processed such
that the AD6672 supports enhanced SNR performance within a
limited region of the Nyquist bandwidth while maintaining an
11-bit output resolution. The NSR block is programmed to provide
a bandwidth of up to 33% of the sample clock. For example, with
a sample clock rate of 250 MSPS, the AD6672 can achieve up to
73.6 dBFS SNR for an 82 MHz bandwidth at 185 MHz fIN.
With the NSR block disabled, the ADC data is provided directly
to the output with an output resolution of 11 bits. The AD6672
can achieve up to 66.6 dBFS SNR for the entire Nyquist bandwidth
when operated in this mode.
AVDD
FUNCTIONAL BLOCK DIAGRAM
AGND
DRVDD
VIN+
VIN–
VCM
PIPELINE
ADC
14 NOISE SHAPED 11
REQUANTIZER
(NSR)
REFERENCE
AD6672
SERIAL PORT
DATA
MULITIPLEXER
AND
LVDS DRIVERS
1-TO-8
CLOCK
DIVIDER
DCO±
0/D0±
D9±/D10±
OR±
SCLK SDIO CSB
Figure 1.
CLK+ CLK–
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD6672
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless
otherwise noted.
Table 2.
Parameter1
Temperature Min Typ Max Unit
SIGNAL-TO-NOISE-RATIO (SNR)
NSR Disabled
fIN = 30 MHz
25°C 66.6 dBFS
fIN = 90 MHz
25°C 66.6 dBFS
fIN = 140 MHz
25°C 66.5 dBFS
fIN = 185 MHz
25°C 66.4 dBFS
Full 65.4
dBFS
fIN = 220 MHz
25°C 66.3 dBFS
NSR Enabled
22% Bandwidth Mode
fIN = 30 MHz
25°C 75.8 dBFS
fIN = 90 MHz
25°C 75.7 dBFS
fIN = 140 MHz
25°C 75.6 dBFS
fIN = 185 MHz
25°C 75.2 dBFS
Full 72.2
dBFS
fIN = 220 MHz
25°C 74.8 dBFS
33% Bandwidth Mode
fIN = 30 MHz
25°C 73.4 dBFS
fIN = 90 MHz
25°C 73.3 dBFS
fIN = 140 MHz
25°C 73.2 dBFS
fIN = 185 MHz
25°C 72.8 dBFS
Full 69.2
dBFS
fIN = 220 MHz
25°C 72.4 dBFS
SIGNAL-TO-NOISE RATIO AND DISTORTION (SINAD)
fIN = 30 MHz
25°C 65.7 dBFS
fIN = 90 MHz
25°C 65.7 dBFS
fIN = 140 MHz
25°C 65.6 dBFS
fIN = 185 MHz
25°C 65.3 dBFS
Full 64.4
dBFS
fIN = 220 MHz
25°C 65.2 dBFS
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
25°C −88 dBc
fIN = 90 MHz
25°C −88 dBc
fIN = 140 MHz
25°C −89 dBc
fIN = 185 MHz
25°C −87 dBc
Full −80 dBc
fIN = 220 MHz
25°C −88 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
25°C 88
dBc
fIN = 90 MHz
25°C 88
dBc
fIN = 140 MHz
25°C 89
fIN = 185 MHz
25°C 87
dBc
Full 80
dBc
fIN = 220 MHz
25°C 88
dBc
Rev. C | Page 5 of 30
5 Page 
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD6672
CLK+ 1
CLK– 2
AVDD 3
OR– 4
OR+ 5
0/D0– (LSB) 6
0/D0+ (LSB) 7
DRVDD 8
AD6672
INTERLEAVED
LVDS
TOP VIEW
(Not to Scale)
24 CSB
23 SCLK
22 SDIO
21 DCO+
20 DCO–
19 D9+/D10+ (MSB)
18 D9–/D10– (MSB)
17 DRVDD
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
ADC Power Supplies
8, 17
DRVDD
3, 27, 28, 31, 32
AVDD
0 AGND,
Exposed Paddle
25
ADC Analog
30
29
26
DNC
VIN+
VIN−
VCM
1
2
Digital Outputs
5
4
7
CLK+
CLK−
OR+
OR−
0/D0+ (LSB)
6 0/D0− (LSB)
10
9
12
11
14
13
16
15
19
18
21
20
SPI Control
23
22
24
D1+/D2+
D1−/D2−
D3+/D4+
D3−/D4−
D5+/D6+
D5−/D6−
D7+/D8+
D7−/D8−
D9+/D10+ (MSB)
D9−/D10− (MSB)
DCO+
DCO−
SCLK
SDIO
CSB
NOTES
1. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE
PACKAGE PROVIDES THE ANALOG GROUND FOR THE
PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
2. DNC = NO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 3. LFCSP Pin Configuration (Top View)
Type
Description
Supply
Supply
Ground
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. The exposed thermal paddle on the bottom of the package provides the
analog ground for the part. This exposed paddle must be connected to ground for proper
operation.
Do Not Connect. Do not connect to this pin.
Input
Input
Output
Input
Input
Differential Analog Input Pin (+).
Differential Analog Input Pin (−).
Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to
ground using a 0.1 μF capacitor.
ADC Clock Input—True.
ADC Clock Input—Complement.
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Overrange indicator—True.
Overrange indicator—Complement.
DDR LVDS Output Data 0—True. The output bit on the rising edge of the data clock output
(DCO) from this output is always a Logic 0 (see Figure 2).
DDR LVDS Output Data 0—Complement. The output bit on the rising edge of the data clock
output (DCO) from this output is always a Logic 0 (see Figure 2).
DDR LVDS Output Data 1/2—True.
DDR LVDS Output Data 1/2—Complement.
DDR LVDS Output Data 3/4—True.
DDR LVDS Output Data 3/4—Complement.
DDR LVDS Output Data 5/6—True.
DDR LVDS Output Data 5/6—Complement.
DDR LVDS Output Data 7/8—True.
DDR LVDS Output Data 7/8—Complement.
DDR LVDS Output Data 9/10—True.
DDR LVDS Output Data 9/10—Complement.
LVDS Data Clock Output—True.
LVDS Data Clock Output—Complement.
Input
Input/output
Input
SPI Serial Clock.
SPI Serial Data I/O.
SPI Chip Select (Active Low).
Rev. C | Page 11 of 30
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD6672.PDF ] | |
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