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PDF SM59D03G2 Data sheet ( Hoja de datos )
| Número de pieza | SM59D03G2 | |
| Descripción | 8-Bits Micro-controller | |
| Fabricantes | SyncMOS | |
| Logotipo |  |
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SyncMOS Technologies International, Inc.
SM59D03G2
8-Bits Micro-controller
8KB+ ISP Flash & 1KB RAM embedded
Product List
Features
z
SM59D03G2L25, 25MHz 8KB+ internal Flash MCU
SM59D03G2C25, 25MHz 8KB+ internal Flash MCU z
Description
z
z
The SM59D03G2 series product is an 8-bit single
chip macro-controller with 8K bytes Flash & 1K
z
z
byte RAM embedded. It is a derivative of the 8052
micro-controller family with a fully compatible
z
instruction sets.
The 8K bytes embedded Flash can be
programmed via a commercial writer or the
external In-System Programming (ISP) function.
z
z
z
The unused Flash on 4K bytes ISP service
Program area can be the memory space for the
z
EEPROM application through the internal ISP.
After programming, the code can be protected to
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prevent illegal read and write.
Its plentiful peripherals can make many
applications easier and more efficient, such
as
z
dual z
DPTR, UART, WDT, Timers, PCA and EEI which
are functionally compatible with most other chips.
SM59D03G2 also provides power saving modes
z
z
(IDLE and STOP), low EMI characteristics, etc. All
of the requirements are considered to achieve the
ideal MCU.
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Ordering Information
yymmv
SM59D03G2ihhkL
z
z
yy: year, mm: month
v: version identifier{ A, B,…}
i: process identifier {L=2.7V~3.6V,C=4.5V~ 5.5V}
hh: working clock in MHz {25}
k: package type postfix {as below table}
L:PB Free identifier
{No text is Non-PB Free，”P” is PB Free}
z
z
z
z
z
Operating Voltage: 2.7V ~ 3.6V or 4.5V ~
5.5V
General 8052 family compatible
12 or 6 clocks per machine cycle
Frequency runs up to 25MHz
8K bytes on chip program Flash
4K bytes In-System Programming(ISP)
and EEPROM capability
768 Bytes on-chip expanded RAM with
disable function
256 Bytes for standard 8052 RAM.
External RAM address up to 64KB
Dual 16-bit Data Pointers (DPTR0 &
DPTR1)
One channel serial peripheral interface
(UART)
Three 16 bit Timers/Counters(Timer 0 , 1,
2)
Four 8-bit I/O ports for PDIP package
Four 8-bit I/O ports + one 4-bit I/O ports for
PLCC or QFP package
Programmable Watchdog Timer (WDT)
Programmable Counter Array (PCA) for
Pulse Width Modulation (PWM), capture
and compare
External interrupt 0, 1 with two priority
level
Expanded External Interrupt (EEI)
interface for eight more external interrupts.
Internal ISP service program space
configurable in N*512 byte (N=0 to 8) size
for IAP application
Direct and simple external ISP without
service program
ALE output select for low EMI
Clock output as the source for next MCU
Power Management Unit ( IDLE and
STOP mod)
Code protection function
Postfix
P
J
Q
Package
40L PDIP
44L PLCC
44L QFP
Pin / Pad
Configuration
Page 2
Page 2
Page 2
Dimension
Page 61
Page 62
Page 63
Contact SyncMOS : www.syncmos.com.tw
6F, No.10-2 Li- Hsin 1st Road , SBIP,
Hsinchu, Taiwan 30078
TEL: 886-3-567-1820 FAX: 886-3-567-1891
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver0.1 SM59D03G2 03/2008
1
1 page  
SyncMOS Technologies International, Inc.
Special Function Register (SFR)
SM59D03G2
8-Bits Micro-controller
8KB+ ISP Flash & 1KB RAM embedded
Address 80h to FFh is the location of SM59D03G2 special function register (SFR). These
locations must be accessed by direct addressing mode only.
The following table gives the SFRs, part of them are identically located and defined as the
general 8052 series:
Table: SM59D03G2 SFR location
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8
KBLS
KBE
KBF
FF
F0 B
ISPFAH ISPFAL ISPFD ISPC
F7
E8 EF
E0 ACC
E7
D8 P4
DF
D0 PSW
D7
C8 T2CON T2MOD RCAP2L RCAP2H TL2
TH2
CF
C0 C7
B8 IP IP1
SCONF
BF
B0 P3
RCON
B7
A8 IE IE1
AF
A0
P2
PCAC1 PCAC2 CC0CON CC1CON CC2CON CC3CON CC4CON
A7
98 SCON SBUF PCACH PCACL CC0DH CC0DL CC1DH CC1DL 9F
90 P1 CC2DH CC2DL CC3DH CC3DL CC4DH CC4DL
97
88
TCON TMOD
TL0
TL1
TH0
TH1 WDTC WDTK
8F
80
P0
SP
DPL
DPH
DPL1 DPH1
DPS
PCON
87
Here is the simple description and initial value of the above SFR. A detailed explanation is
given in later sections.
Table：SFR description and initial value
Register Location Initial value
Description
P0 80h
FFh Port 0
SP 81h
07h Stack Pointer
DPL 82h
00h Data Pointer Low byte
DPH
83h
00h Data Pointer High byte
DPL1
84h
00h Data Pointer 1 Low byte
DPH1
85h
00h Data Pointer 1 High byte
DPS
PCON
86h
87h
00h Data Pointer select
00h Power control register
TCON
88h
00h Timer control register
TMOD
TL0
89h
8Ah
00h Timer Mode
00h Timer 0 low byte
TL1 8Bh
00h Timer 1 low byte
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver0.1 SM59D03G2 03/2008
5
5 Page 
SyncMOS Technologies International, Inc.
SM59D03G2
8-Bits Micro-controller
8KB+ ISP Flash & 1KB RAM embedded
Data Transfers Instructions
MOV
A, Rn
MOV
A, direct
MOV
A, @Ri
MOV
A, #data
MOV
Rn, A
MOV
Rn, direct
MOV
Rn, #data
MOV
direct, A
MOV
direct, Rn
MOV
direct, direct
MOV
direct, @Ri
MOV
direct, #data
MOV
@Ri, A
MOV
@Ri, direct
MOV
@Ri, #data
MOV
DPTR, #data16
MOVC
A, @A+DPTR
MOVC
A, @A+PC
MOVX
A, @Ri
MOVX
A, @DPTR
MOVX
@Ri, A
MOVX
@DPTR, A
PUSH
direct
POP
direct
XCH
A,Rn
XCH
A, direct
XCH
A, @Ri
XCHD
A, @Ri
Boolean Instructions
CLR
C
CLR
bit
SETB
C
SETB
bit
CPL C
CPL bit
ANL C, bit
ANL C, /bit
ORL
C, bit
ORL
C, /bit
MOV
C, bit
MOV
bit, C
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
Jump Instructions
ACALL
addr11
LCALL
addr16
RET
RETI
AJMP
addr11
LJMP
addr16
SJMP
rel
JMP
@A+DPTR
JZ rel
JNZ rel
CJNE
A, direct,rel
CJNZ
A, #data,rel
CJNZ
Rn, #data,rel
CJNZ
@Ri, #data,rel
DJNZ
Rn, rel
DJNZ
direct, rel
NOP
A = Rn
A = direct
A = <@Ri>
A = #data
Rn = A
Rn = direct
Rn = #data
direct = A
direct = Rn
direct = direct
direct = <@Ri>
direct = #data
<@Ri> = A
<@Ri> = direct
<@Ri> = #data
DPTR = #data16
A = code memory[A+DPTR]
A = code memory[A+PC]
A = external memory[Ri] (8-bits address)
A = external memory[DPTR] (16-bits address)
external memory[Ri] = A (8-bits address)
external memory[DPTR] = A (16-bits address)
INC SP: MOV “@’SP’, < direct >
MOV < direct >, “@SP”: DEC SP
ACC and < Rn > exchange data
ACC and < direct > exchange data
ACC and < Ri > exchange data
ACC and @Ri exchange low nibbles
C=0
bit = 0
C=1
bit = 1
C = /C
bit = /bit
C = C .AND. bit
C = C .AND. /bit
C = C .OR. bit
C = C .OR. /bit
C = bit
bit = C
Jump if C= 1
Jump if C= 0
Jump if bit = 1
Jump if bit = 0
Jump if C = 1
Call Subroutine only at 2k bytes Address
Call Subroutine in max 64K bytes Address
Return from subroutine
Return from interrupt
Jump only at 2k bytes Address
Jump to max 64K bytes Address
Jump on at 256 bytes
Jump to A+ DPTR
Jump if A = 0
Jump if A ≠ 0
Jump if A ≠ < direct >
Jump if A ≠ < #data >
Jump if Rn ≠ < #data >
Jump if @Ri ≠ < #data >
Decrement and jump if Rn not zero
Decrement and jump if direct not zero
No Operation
11
21
11
21
11
22
21
21
22
32
22
21
11
22
21
32
12
12
12
12
12
12
22
22
11
21
11
11
11
21
11
21
11
21
22
22
22
22
21
22
22
22
32
32
32
22
32
12
12
22
32
22
12
22
22
32
32
32
32
22
32
11
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver0.1 SM59D03G2 03/2008
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SM59D03G2.PDF ] | |
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