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PDF MP6532 Data sheet ( Hoja de datos )
| Número de pieza | MP6532 | |
| Descripción | Three-Phase Brushless DC Motor Pre-Driver | |
| Fabricantes | MPS | |
| Logotipo |  |
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The Future of Analog IC Technology
MP6532
5V to 60V, Three-Phase Brushless
DC Motor Pre-Driver
DESCRIPTION
The MP6532 is a gate driver IC designed for
three-phase brushless DC motor driver
applications. It is capable of driving three half
bridges consisting of six N-channel power
MOSFETs up to 60V.
The MP6532 uses a bootstrap capacitor to
generate a supply voltage for the high-side
MOSFET driver. An internal trickle-charge circuit
maintains sufficient gate driver voltage at 100%
duty cycle.
Internal safety features include programmable
over-current protection, a motor start-up current
limit, adjustable dead-time control, UVLO, and
thermal shutdown.
The device has three Hall-element inputs.
Commutation logic is determined by three Hall-
element inputs spaced at 120°. The PWM, DIR,
and nBRAKE inputs are used to control motor
speed, direction, and brake engagement.
The MP6532 is available in 28-pin,
9.7mm×6.4mm TSSOP-EP and 4mmx4mm QFN-
28 package with an exposed thermal pad on the
back.
FEATURES
Wide 5V to 60V Input Voltage Range
Hall Signal Interface
Bootstrap Gate Driver with Trickle-Charge
Circuit Supports 100% Duty Cycle Operation
Low-Power Sleep Mode for Battery-
Powered Applications
Programmable Over-Current Protection of
External MOSFETs
Adjustable Dead-Time Control to Prevent
Shoot-Through
PWM Speed-Control Input
Brake Input
Motor Start-Up Current Limit
Thermal Shutdown and UVLO Protection
Fault Indication Output
Thermally Enhanced Surface-Mount
Package
APPLICATIONS
Three-Phase Brushless DC Motors and
Permanent Magnet Synchronous Motors
Power Drills
Impact Drivers
E-Bike
All MPS parts are lead-free, halogen-free and adhere to the RoHS directive.
For MPS green status, please visit MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MP6532 Rev. 1.11
www.MonolithicPower.com
9/6/2015
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
1
1 page  
MP6532 – 5V TO 60V, THREE PHASE BLDC MOTOR PRE-DRIVER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 24V, TA = 25°C, unless otherwise noted.
Parameter
Symbol
Condition
Min
Gate Drive
Bootstrap Diode Forward
Voltage
VREG Output Voltage
Gate Drive Pull Up
Resistance
VFBOOT
VREG
RUP
ID=10mA
ID=100mA
VIN=5.5V-60V,
TJ =25°C
VIN=5V
VDS=1V
10
2xVIN-1
HS Gate Drive Pull Down
Resistance
RHS-DN
VDS=1V
1.2
LS Gate Drive Pull Down
Resistance
RLS-DN
VDS=1V
1
LS Passive Pull Down
Resistance
RLS-PDN
LS Automatic Turn On Time
tLS
Charge Pump Frequency
Dead Time
fCP
tDEAD
Leave DT Open
RDT=200kΩ
DT tied to GND
Typ
11.5
8
590
1.8
110
6
0.74
30
Max
0.9
1.3
12.8
4.3
5
Units
V
V
V
Ω
Ω
Ω
kΩ
µs
kHz
µs
µs
ns
MP6532 Rev. 1.11
www.MonolithicPower.com
9/6/2015
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
5
5 Page 
MP6532 – 5V TO 60V, THREE PHASE BLDC MOTOR PRE-DRIVER
OPERATION
The MP6532 is a three-phase BLDC motor pre-
driver that can drive three half bridges with a
0.8A source and a 1A sink current capability over
a wide input voltage range of 5V to 60V. It is
designed for use in battery-powered equipment.
The MP6532 features a low-power sleep mode,
which disables the device and draws a very low
supply current.
The MP6532 provides several flexible functions,
such as adjustable dead-time control and over-
current protection, which allow the device to
cover a wide range of application fields.
nFAULT
nFAULT reports to the system when a fault
condition (such as OCP and OTP) is detected.
nFAUlt can be an open-drain output, and it is
driven low once a fault condition occurs. If the
fault condition is released, nFAULT is pulled high
by an external pull-up resistor.
Over-Current Protection
To protect the power stage from damage due to
high currents, a VDS sensing circuitry is
implemented in the MP6532. Based on RDS-ON of
the power MOSFETs and the maximum allowed
IDS, a voltage threshold can be calculated which
triggers the OC protection feature when
exceeded. This voltage threshold level is
programmable through the OC_REF terminal by
applying an external reference voltage with a
DAC. Once an OCP event is detected, MP6532
will enter a latched fault state and disable all
functions. MP6532 will stay latched off until it is
reset by nSLEEP or UVLO.
Motor Startup Current Limit
MP6532 limits the motor startup current by
monitoring the voltage at LSS pin. When the
voltage at LSS exceeds the current limit
threshold of 0.5V, the high side will turn off and
the corresponding low side turns on for a fixed off
time. After the fixed off time, the high side will
turn back on and the cycle repeats until LSS no
longer exceeds the current limit threshold. The
current limit level is selected by the value of the
current sense resistor at LSS pin.
OCP Deglitch Time
Usually, there is a current spike during the
switching transition due to the body diode’s
reverse-recovery current or the distributed
inductance or capacitance. This current spike
requires filtering to prevent it from erroneously
triggering OCP and shutting down the external
MOSFET. An internal fixed deglitch time (tOC)
blanks the output of the VDS monitor when the
outputs are switched (which is also the minimum
on time for the MOSFET).
Dead Time Adjustment
To prevent shoot-through in any phase of the
bridge, it is necessary to have a dead time (tDEAD)
between a high- or low-side turn-off and the next
complementary turn-on event. The dead time for
all three phases is set by a single dead-time
resistor (RDT) between DT and ground with
Equation(1):
tDEAD(nS) = 3.7*R(kΩ)
(1)
If DT is tied to GND directly, an internal minimum
dead time (30ns) will be applied. Leaving DT
open generates a 6µs dead time.
Input UVLO Protection
If at any time the voltage on VIN falls below the
under-voltage lockout threshold voltage, all
circuitry in the device is disabled and the internal
logic will be reset. Operation will resume when
VIN rises above the UVLO threshold.
Thermal Shutdown
If the die temperature exceeds safe limits, the
MP6532 enters a latched fault state similar to an
OCP event, and nFAULT is driven low. Only
resetting by nSLEEP or UVLO will unlatch the
device from an OTP fault lockout.
Input Logic
Driving nSLEEP low will put the device into a
low-power sleep state. In this state, all the
internal circuits are disabled. All inputs are
ignored when nSLEEP is active low. When
exiting sleep mode, a brief time period
(approximately 1ms) must pass before issuing a
PWM command. This time period allows the
internal circuitry to stabilize.
MP6532 Rev. 1.11
www.MonolithicPower.com
9/6/2015
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet MP6532.PDF ] | |
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