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PDF RT7302 Data sheet ( Hoja de datos )

Número de pieza RT7302
Descripción Primary-Side-Regulation Dimmable LED Driver Controller
Fabricantes Richtek 
Logotipo Richtek Logotipo



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®
RT7302
Primary-Side-Regulation Dimmable LED Driver Controller
with Active PFC
General Description
The RT7302 is a constant current LED driver with active
power factor correction. It supports high power factor
across a wide range of line voltages, and it drives the
converter in the Quasi-Resonant (QR) mode to achieve
higher efficiency. By using Primary Side Regulation (PSR),
the RT7302 controls the output current accurately without
a shunt regulator and an opto-coupler at the secondary
side, reducing the external component count, the cost,
and the volume of the driver board.
The RT7302 is designed to be compatible with PWM
Dimming. The output current can be modulated by the
duty ratio of the external PWM dimming signal.
An in-house design High Voltage (HV) start-up device is
integrated in the RT7302 to minimize the power loss and
shorten the start-up time.
The RT7302 embeds comprehensive protection functions
for robust designs, including LED open-circuit protection,
LED short-circuit protection, output diode short-circuit
protection, VDD Under-Voltage Lockout (UVLO), VDD
Over-Voltage Protection (VDD OVP), Over-Temperature
Protection (OTP), and cycle-by-cycle current limitation.
Features
Tight LED Current Regulation
No Opto-Coupler and TL431 Required
Power Factor Correction (PFC)
Compatible with PWM Dimming
Built-in HV Start-up Device
Quasi-Resonant
Maximum/Minimum Switching Frequency
Clamping
Input Voltage Feed-Forward Compensation
Maximum/Minimum On-Time Limitation
Wide VDD Voltage Range (up to 25V)
Multiple Protection Features
LED Open-Circuit Protection
LED Short-Circuit Protection
Output Diode Short-Circuit Protection
VDD Under-Voltage Lockout
VDD Over-Voltage Protection
Over-Temperature Protection
Cycle-by-Cycle Current Limit
RoHS Compliant and Halogen Free
Applications
AC/DC LED Lighting driver
Simplified Application Circuit
Flyback Converter
Buck-Boost Converter
Line
Neutral
BD
CSIN RM1 RHV
RT7302
HV
MULT
GD
RM2
CS
RPC
TX1
DOUT
VOUT+
COUT
VOUT-
Q1
COMP
RCS
CCOMP
GND
VDD
ZCD
DAUX
CVDD
RZCD1
RZCD2
Line
Neutral
BD
CSIN RM1 RHV
RT7302
HV
MULT
GD
RM2
CS
RPC
TX1
Q1
DOUT
VOUT-
COUT
VOUT+
COMP
RCS
CCOMP
GND
VDD
ZCD
DAUX
CVDD
RZCD1
RZCD2
Copyright ©2015 Richtek Technology Corporation. All rights reserved.
DS7302-03 May 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1

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RT7302 pdf
RT7302
Quasi-Resonant Operation
For improving converter's efficiency, the RT7302 detects
valleys of the Drain-to-Source voltage (VDS) of main switch
and turns on it near the selected valley. For the valley
detections, a pulse of the valley signalis generated
after a 500ns (typ.) delay time which starts at which the
voltage (VZCD) on ZCD pin goes down and reaches the
voltage threshold (VZCDT, 0.4V typ.). During the rising of
the VZCD, the VZCD must reach the voltage threshold
(VZCDA, 0.5V typ.). Otherwise, no pulse of the valley
signalis generated. Moreover, if the timing when the
falling VZCD reaches VZCDT is not later than a mask time
(tMASK, 2μs typ.) then the valley signal will be masked and
regards as no valley, as shown in Figure 4.
PWM
VZCD
VZCDA
VZCDT
Valley
Signal
500ns
tMASK
Figure 4. Valley Signal Generating Method
Figure 5 illustrates how valley signal triggers PWM. If no
valley signal is detected for a long time, the next PWM is
triggered by a starter circuit at the end of the interval (tSTART,
130μs typ.) which starts at the rising edge of the previous
PWM signal. A blanking time (tS(MIN), 8.5μs typ.), which
starts at the rising edge of the previous PWM signal, limits
minimum switching period. When the tS(MIN) interval is
on-going, all of valley signals are not allowed to trigger
the next PWM signal. After the end of the tS(MIN) interval,
the coming valley will trigger the next PWM signal. If one
or more valley signals are detected during the tS(MIN)
interval and no valley is detected after the end of the tS(MIN)
interval, the next PWM signal will be triggered
automatically at the end of the tS(MIN) + 5μs (typ.).
Valley
Signal
PWM
Valley
Signal
tSTART
PWM
Valley
Signal
tS(MIN)
……
PWM
Valley
Signal
tS(MIN)
……
PWM
tS(MIN)
5µs
Figure 5. PWM Triggered Method
HV Start-up Device
An in-house design 500V start-up device is integrated in
the RT7302 to minimize the power loss and shorten the
start-up time. The HV start-up device will be turned on
during start-up period and be turned off during normal
operation. It guarantees fast start-up time and no power
loss in this path during normal operation. A 10kΩ resistor
is recommended to be connected in series with HV pin.
Feed-Forward Compensation
The MULT pin is a high impedance input pin used to detect
the line input voltage. A proper voltage divider and a
capacitor should be applied to sense the rectified input
voltage at the output of bridge diode rectifier. Since the
MULT voltage is proportional to the rectified input voltage,
it is used to generate a feed-forward signal, the peak of
the MULT voltage, to compensate the slope of the ramp,
Copyright ©2015 Richtek Technology Corporation. All rights reserved.
DS7302-03 May 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5

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RT7302 arduino
RT7302
100
90
80
70
60
50
40
30
-50
ICOMP(MAX) vs. Temperature
-25 0 25 50 75 100 125
Temperature (°C)
tSTART vs. Temperature
150
140
130
120
110
100
90
-50
-25
0 25 50 75
Temperature (°C)
100 125
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
-50
VCS_CL vs. Temperature
-25 0
25 50 75 100
Temperature (°C)
125
Copyright ©2015 Richtek Technology Corporation. All rights reserved.
DS7302-03 May 2015
tON(MIN) vs. Temperature
3.0
2.8
2.6
2.4
2.2
2.0
-50
-25
0 25 50 75
Temperature (°C)
100 125
VCS_SD vs. Temperature
1.8
1.7
1.6
1.5
1.4
1.3
1.2
-50
-25
0 25 50 75 100 125
Temperature (°C)
0.022
KPC vs. Temperature
0.021
0.020
0.019
0.018
0.017
0.016
-50
-25
0 25 50 75
Temperature (°C)
100 125
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11

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