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PDF RT9627A Data sheet ( Hoja de datos )
| Número de pieza | RT9627A | |
| Descripción | High Voltage Synchronous Rectified Dual-Channel Buck MOSFET Driver | |
| Fabricantes | Richtek | |
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®
RT9627A
High Voltage Synchronous Rectified Dual-Channel Buck
MOSFET Driver for Notebook Computer
General Description
The RT9627A is a high frequency, dual-channel driver
specifically designed to drive two power N-MOSFETs in
each channel of a synchronous-rectified Buck converter
topology. It is especially suited for mobile computing
applications that require high efficiency and excellent
thermal performance. This driver, combined with Richtek's
series of multi-phase Buck PWM controllers, provides a
complete core voltage regulator solution for advanced
microprocessors.
The drivers are capable of driving a 3nF load with fast
rising/falling time and fast propagation delay. This device
implements bootstrapping on the upper gates with only a
single external capacitor. This reduces implementation
complexity and allows the use of higher performance, cost
effective, N-MOSFETs. Adaptive shoot through protection
is integrated to prevent both MOSFETs from conducting
simultaneously.
Features
Dual-Channel Driver
Each Channel Drives Two N-MOSFETs
Adaptive Shoot-Through Protection
0.5Ω On-Resistance, 4A Sink Current Capability
Supports High Switching Frequency
Tri-State PWM Input for Power Stage Shutdown
Output Disable Function
Integrated Boost Switch
Low Bias Supply Current
VCC POR Feature Integrated
RoHS Compliant and Halogen Free
Applications
Core Voltage Supplies for Intel® / AMD® Mobile
Microprocessors
High Frequency Low Profile DC/DC Converters
High Current Low Output Voltage DC/DC Converters
High Input Voltage DC/DC Converters
Simplified Application Circuit
VCC
R1 RT9627A
VCC UGATE1
C1
BOOT1
PHASE1
Enable
EN
LGATE1
VIN
R2 C2
QUG1
CIN
QLG1
L2
C3
VCORE
COUT
R5
PWM1
PWM2
PWM1
UGATE2
PWM2 BOOT2
PHASE2
GND LGATE2
R5 C15
QUG2
VIN
L3
QLG2
C16
R8
Copyright ©2014 Richtek Technology Corporation. All rights reserved.
DS9627A-02 August 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
1 page  
RT9627A
Parameter
PWMx Input
Symbol
Input Current
IPWM
PWMx Tri-State Rising Threshold VPWMH
PWMx Tri-State Falling Threshold VPWML
Tri-State Shutdown Hold-off Time tSHD_Tri
EN Input
EN Input Voltage
Switching Time
Logic-High
Logic-Low
VENH
VENL
UGATEx Rise Time
tUGATEr
UGATEx Fall Time
tUGATEf
LGATEx Rise Time
tLGATEr
LGATEx Fall Time
UGATEx Turn-Off Propagation
Delay
tLGATEf
tPDLU
LGATEx Turn-Off Propagation
Delay
tPDLL
UGATEx Turn-On Propagation
Delay
tPDHU
LGATEx Turn-On Propagation
Delay
tPDHL
UGATEx/LGATEx Tri-State
Propagation Delay
tPTS
Output
UGATEx Driver Source Resistance RUGATEsr
UGATEx Driver Source Current IUGATEsr
UGATEx Driver Sink Resistance RUGATEsk
UGATEx Driver Sink Current
IUGATEsk
LGATEx Driver Source Resistance RLGATEsr
LGATEx Driver Source Current
LGATEx Driver Sink Resistance
LGATEx Driver Sink Current
ILGATEsr
RLGATEsk
ILGATEsk
Test Conditions
VPWM = 5V
VPWM = 0V
3nF load
3nF load
3nF load
3nF load
Outputs Unloaded
Outputs Unloaded
Outputs Unloaded
Outputs Unloaded
Outputs Unloaded
100mA Source Current
VUGATE VPHASE = 2.5V
100mA Sink Current
VUGATE VPHASE = 2.5V
100mA Source Current
VLGATE = 2.5V
100mA Sink Current
VLGATE = 2.5V
Min Typ Max Unit
-- 174 --
-- 174 --
3.5 3.8 4.1
0.7 1 1.3
100 175 250
A
V
V
ns
2 -- --
V
-- -- 0.5
-- 8 -- ns
-- 8 -- ns
-- 8 -- ns
-- 4 -- ns
-- 35 -- ns
-- 35 -- ns
-- 20 -- ns
-- 20 -- ns
-- 35 -- ns
-- 1 --
-- 2 --
-- 1 --
-- 2 --
-- 1 --
-- 2 --
-- 0.5 --
-- 4 --
A
A
A
A
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution recommended. The human body mode is a 100pF capacitor is
charged through a 1.5kΩ resistor into each pin.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright ©2014 Richtek Technology Corporation. All rights reserved.
DS9627A-02 August 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
5 Page 
RT9627A
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WDFN-12L 3x3 package, the thermal resistance, θJA, is
30.5°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (30.5°C/W) = 3.28W for
WDFN-12L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. The derating curve in Figure 3 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
3.6
Four-Layer PCB
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0
25 50 75 100
Ambient Temperature (°C)
125
Figure 3. Derating Curve of Maximum Power Dissipation
Layout Considerations
Figure 4 shows the schematic circuit of a synchronous
Buck converter to implement the RT9627A.
VBAT L1
CIN1 CIN2
VCORE
COUT
QUGx
Lx
QLGx
VIN
BOOTx
CB VCC
RT9627A
PHB83N03LT
UGATEx
PWMx
PHASEx
EN
PHB95N03LT LGATEx GND
5V
R1
C1
PWM
Signal
5V
Figure 4. Synchronous Buck Converter Circuit
When layout the PCB, it should be very careful. The power
circuit section is the most critical one. If not configured
properly, it will generate a large amount of EMI. The
junction of QUGx, QLGx, Lx should be very close.
Next, the trace from UGATEx, and LGATEx should also
be short to decrease the noise of the driver output signals.
PHASEx signals from the junction of the power MOSFET,
carrying the large gate drive current pulses, should be as
heavy as the gate drive trace. The bypass capacitor C1
should be connected to GND directly. Furthermore, the
bootstrap capacitors (CB) should always be placed as close
to the pins of the IC as possible.
Copyright ©2014 Richtek Technology Corporation. All rights reserved.
DS9627A-02 August 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet RT9627A.PDF ] | |
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