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PDF IS49NLS96400 Data sheet ( Hoja de datos )
| Número de pieza | IS49NLS96400 | |
| Descripción | Separate I/O RLDRAM 2 Memory | |
| Fabricantes | Integrated Silicon Solution | |
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IS49NLS96400,IS49NLS18320
576Mb (x9, x18) Separate I/O RLDRAM 2 Memory
FEATURES
ADVANCED INFORMATION
JULY 2012
533MHz DDR operation (1.067 Gb/s/pin data
rate)
38.4 Gb/s peak bandwidth (x18 Separate I/O at
533 MHz clock frequency)
Reduced cycle time (15ns at 533MHz)
32ms refresh (16K refresh for each bank; 128K
refresh command must be issued in total each
32ms)
8 internal banks
Non‐multiplexed addresses (address
multiplexing option available)
SRAM‐type interface
Programmable READ latency (RL), row cycle
time, and burst sequence length
Balanced READ and WRITE latencies in order to
optimize data bus utilization
Data mask signals (DM) to mask signal of
WRITE data; DM is sampled on both edges of
DK.
Differential input clocks (CK, CK#)
Differential input data clocks (DKx, DKx#)
On‐die DLL generates CK edge‐aligned data and
output data clock signals
Data valid signal (QVLD)
HSTL I/O (1.5V or 1.8V nominal)
25‐60Ω matched impedance outputs
2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
On‐die termination (ODT) RTT
IEEE 1149.1 compliant JTAG boundary scan
Operating temperature:
Commercial
(TC = 0° to +95°C; TA = 0°C to +70°C),
Industrial
(TC = ‐40°C to +95°C; TA = ‐40°C to +85°C)
OPTIONS
Package:
144‐ball FBGA (leaded)
144‐ball FBGA (lead‐free)
Configuration:
64Mx9
32Mx18
Clock Cycle Timing:
Speed Grade
‐18
‐25E ‐25 ‐33 Unit
tRC 15 15 20 20 ns
tCK 1.875 2.5 2.5 3.3 ns
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
RLDRAM is a registered trademark of Micron Technology, Inc.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00E, 06/20/2012
1
1 page  
IS49NLS96400,IS49NLS18320
2 Electrical Specifications
2.1 Absolute Maximum Ratings
Item
Min
Max
Units
I/O Voltage
0.3
VDDQ + 0.3
V
Voltage on VEXT supply relative to VSS
0.3 2.8 V
Voltage on VDD supply relative to VSS
0.3 2.1 V
Voltage on VDDQ supply relative to VSS
0.3 2.1 V
Note: Stress greater than those listed in this table may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2.2 DC Electrical Characteristics and Operating Conditions
Description
Conditions Symbol
Min
Max
Units Notes
Supply voltage
VEXT 2.38
2.63
V
Supply voltage
VDD 1.7
1.9 V 2
Isolated output buffer supply
Reference voltage
Termination voltage
Input high voltage
Input low voltage
Output high current
VOH = VDDQ/2
VDDQ
VREF
VTT
VIH
VIL
IOH
1.4
0.49 x VDDQ
0.95 x VREF
VREF + 0.1
VSSQ 0.3
(VDDQ/2)/
(1.15 x RQ/5)
VDD
0.51 x VDDQ
1.05 x VREF
VDDQ + 0.3
VREF 0.1
(VDDQ/2)/
(0.85 x RQ/5)
V 2,3
V 4,5,6
V 7,8
V 2
V 2
A
9, 10,
11
Output low current
VOL = VDDQ/2
IOL
(VDDQ/2)/
(1.15 x RQ/5)
(VDDQ/2)/
(0.85 x RQ/5)
A
9, 10,
11
Clock input leakage current
Input leakage current
Output leakage current
0V ≤ VIN ≤ VDD
0V ≤ VIN ≤ VDD
0V ≤ VIN ≤ VDDQ
ILC
ILI
ILO
5
5
5
5 µA
5 µA
5 µA
Reference voltage current
IREF 5
5 µA
Notes:
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH (AC) ≤ VDD + 0.7V for t ≤ tCK/2. Undershoot: VIL (AC) ≥ –0.5V for t ≤ tCK/2. During normal operation, VDDQ must not exceed VDD. Control input signals
may not have pulse widths less than tCK/2 or operate at frequencies exceeding tCK (MAX).
3. VDDQ can be set to a nominal 1.5V ± 0.1V or 1.8V ± 0.1V supply.
4. Typically the value of VREF is expected to be 0.5 x VDDQ of the transmitting device. VREF is expected to track variations in VDDQ.
5. Peak‐to‐peak AC noise on VREF must not exceed ±2 percent VREF (DC).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak‐to‐peak noise (non‐common mode) on VREF
may not exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±2 percent VDDQ/2 for DC error and an additional ±2 percent VDDQ/2 for AC noise.
This measurement is to be taken at the nearest VREF bypass capacitor.
7. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
8. On‐die termination may be selected using mode register A9 (for non‐multiplexed address mode) or Ax9 (for multiplexed address mode). A resistance RTT from
each data input signal to the nearest VTT can be enabled. RTT = 125–185Ω at 95°C TC.
9. IOH and IOL are defined as absolute values and are measured at VDDQ /2. IOH flows from the device, IOL flows into the device.
10. If MRS bit A8 or Ax8 is 0, use RQ = 250Ω in the equation in lieu of presence of an external impedance matched resistor.
2.3 Capacitance
(TA = 25 °C, f = 1MHz)
Parameter
Symbol
Test Conditions
Min
Max Units
Address / Control Input capacitance
CIN
I/O, Output, Other capacitance (D, Q, DM, QK, QVLD)
CIO
Clock Input capacitance
CCLK
JTAG pins
CJ
Note. These parameters are not 100% tested and capacitance is not tested on ZQ pin.
VIN=0V
VIO=0V
VCLK=0V
VJ=0V
1.5 2.5 pF
3.5 5 pF
2 3 pF
2 5 pF
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00E, 06/20/2012
5
5 Page 
IS49NLS96400,IS49NLS18320
3 Functional Descriptions
3.1 Power‐up and Initialization (1)
The RLDRAM 2 Memory must be powered‐up and initialized using the specific steps listed below:
1. Apply power by ramping up supply voltages VEXT, VDD, VDDQ, VREF, and VTT. Apply VDD and VEXT before or at the same time as VDDQ (2).
Power‐up sequence begins when both VDD and VEXT approach their nominal levels. Afterwards, apply VDDQ before or at the same
time as VREF and VTT. Once the supply voltages are stable, clock inputs CK/CK# and DK/DK# can be applied. Register NOP
commands to the control pins to avoid issuing unwanted commands to the device.
2. Keep applying stable conditions for a minimum of 200 µs.
3. Register at least three consecutive MRS commands consisting of two or more dummy MRS commands and one valid MRS
command. Timing parameter tMRSC is not required to be met during these consecutive MRS commands but asserting a LOW logic
to the address signals is recommended.
4. tMRSC timing delay after the valid MRS command, Auto Refresh commands to all 8 banks and 1,024 NOP commands must be
issued prior to normal operation. The Auto Refresh commands to the 8 banks can be issued in any order with respect to the
1,024 NOP commands. Please note that the tRC timing parameter must be met between an Auto Refresh command and a valid
command in the same bank.
5. The device is now ready for normal operation.
Notes:
1. Operational procedure other than the one listed above may result in undefined operations and may permanently damage the device.
2. VDDQ can be applied before VDD but will result in all D and Q data pins, DM, and other pins with an output driver to go logic HIGH (instead of tri‐state) and will
remain HIGH until the VDD is the same level as VDDQ. This method is not recommended to avoid bus conflicts during the power‐up.
3.2 Power‐up and Initialization Flowchart
Notes:
1. The supply voltages can be ramped up simultaneously.
2. The dummy and valid MRS commands must be issued in consecutive clock cycles. At least two dummy MRS commands are required. It is recommended to
assert a LOW logic on the address signals during the dummy MRS commands.
3. The Auto Refresh commands can be issued in any order with respect to the 1,024 NOP commands. However, timing parameter tRC must be met before issuing
any valid command in a bank after an AREF command to the same bank has been issued.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00E, 06/20/2012
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS49NLS96400.PDF ] | |
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