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PDF RP6104 Data sheet ( Hoja de datos )
| Número de pieza | RP6104 | |
| Descripción | Wide Input Range Synchronous Buck DC/DC PWM Controller | |
| Fabricantes | RichPower | |
| Logotipo |  |
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Preliminary
RP6104
Wide Input Range Synchronous Buck DC/DC PWM
Controller
General Description
The RP6104 is a fixed-frequency PWM controller with
integrated MOSFET drivers for single power rail
synchronous single-phase buck converter. This part
features an internal regulator that allows wide input voltage
range operation. The RP6104 utilizes voltage-mode control
with internal compensation to simplify the converter
design. An internal 0.8V reference voltage allows low
output voltage application. The switching frequency is fixed
at 600kHz to reduce the external passive component size
to save board space. The RP6104 provides under voltage
protection, current limit, over current protection and over
temperature protection. The low-side MOSFET RDS(ON) is
used to sense the inductor current for over current
protection.
Ordering Information
RP6104
Package Type
SP : SOP-8 (Exposed Pad-Option 1)
Operating Temperature Range
G : Green (Halogen Free with Commer-
cial Standard)
Features
10V to 23V Wide Input Voltage Range
0.8V Internal Reference
Internal Soft Start
High DC Gain Voltage Mode PWM Control
Fixed 600kHz Switching Frequency
Fast Transient Response
Fully Dynamic 0 to 80% Duty Cycle
Over Current Protection
Under Voltage Protection
Over Temperature Protection
RoHS Compliant
Applications
Set-top Box Power Supplies
PC Subsystem Power Supplies
Cable Modems, DSL Modems
DSP and Core Communication Processor Power
Supplies
Memory Power Supplies
Personal Computer Peripherals
Industrial Power Supplies
Low Voltage Distributed Power Supplies
Note :
Richpower Green products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Pin Configurations
(TOP VIEW)
PHASE
UGATE
GND
LGATE
8
27
GND
3 96
45
BOOT
VIN
FB
VCC
SOP-8 (Exposed Pad)
RP6104-01P Jan 2010
1
1 page  
Preliminary
RP6104
Parameter
MOSFET Gate Driver
UGATE Drive Source
UGATE Drive Sink
LGATE Drive Source
LGATE Drive Sink
UGATE Drive Source
UGATE Drive Sink
LGATE Drive Source
LGATE Drive Sink
Protection
Over Current Threshold
Maximum Duty Cycle
UVP Threshold
Soft Start
Soft Start Interval
Symbol
Test Conditions
RUGATEsr
RUGATEsk
RLGATEsr
RLGATEsk
IUGATEsr
IUGATEsk
ILGATEsr
ILGATEsk
VBOOT − PHASE = 5V
VBOOT − VUGATE = 1V
VUGATE −PHASE = 1V
VBOOT − PHASE = 5V
VCC − VLGATE = 1V,
VLGATE = 1V
VBOOT −VUGATE = 5V
VUGATE −PHASE = 5V
VVCC −VLGATE = 5V
VLGATE −GND = 5V
VOC Sense Phase Pin Voltage
FB Falling
TSS
Min Typ Max Units
-- 3 4.5
-- 2 3
-- 4 6
-- 2 4
-- 0.72 --
-- 0.82 --
-- 0.65 --
-- 1.18 --
Ω
Ω
Ω
Ω
A
A
A
A
-- −250 --
mV
-- 80 -- %
-- 0.5 0.6 V
1 3 6 ms
Note 1. Stresses listed as the above “ Absolute Maximum Ratings” may cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution is recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test
board of JEDEC 51-7 thermal measurement standard. The case position of θJC is on the exposed pad of SOP-
8 (Exposed Pad) package.
Note 5. Guarantee by design.
RP6104-01P Jan 2010
5
5 Page 
Preliminary
RP6104
Referring to Figure 5, the location of pole and zero of the
LC filter and the compensation network can be determined
using the following equations. The inductor and the output
capacitor create a double pole at FLC :
FLC =
1
2π × L × COUT
The equivalent series resistance (ESR) of the output
capacitor creates a zero at FESR :
FESR
=
1
2π ×ESR × COUT
The internal compensation network introduces a zero at
FZ1 :
FZ1 =
1
2π ×RS × CS
The internal compensation network also introduces a pole
at FP2 :
FP2
=
1
2π
× RS
×
CS
CS
× CP
+ CP
The external R3 and C3 introduces a zero at FZ2 :
FZ2
=
1
2π × (R3 + R2)× C3
The external R3 and C3 introduces a pole at FP1 :
FP1
=
1
2π × (R3 + R1 // R2)× C3
Since the internal compensation values are given, the close
loop crossover frequency and phase margin can be
obtained after inductance and capacitance are determined.
External R3 and C3 are used to adjust the crossover
frequency and phase margin. The typical design procedure
is described as follows.
Step 1 : Collect system parameters such as switching
frequency, input voltage, output voltage, output voltage
ripple, and full load current.
Step 2 : Determine the output inductance value. The
recommended inductor ripple current is between 10% and
30% of the full load output current. The inductance can be
calculated using the following equation.
VIN − VOUT
IFULL_LOAD × 0.3
×
VOUT
VIN
×
1
FSW
<L
<
IFUVLILN_L−OVAODU×T0.1 ×
VOUT
VIN
×
1
FSW
Step 3 : Determine the output capacitance and the ESR.
Neglecting the equivalent series inductance of the output
capacitor, the output capacitance COUT can be
approximately determined using the following equations.
VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C)
VRIPPLE(ESR) = IRIPPLE ×ESR
VRIPPLE(C)
=
IRIPPLE
8 × COUT ×FSW
Step 4 : Calculate the crossover frequency, phase margin
and check stability.
Calculate the frequency of FLC, FESR, FZ1, FZ2, FP1 and
FP2 with selected inductance, capacitance and ESR. Then
plot the Bode diagram of close loop gain to check crossover
frequency and phase margin. In general, the crossover
frequency FC is between 1/10 and 1/5 of the switching
frequency (60kHz to 120kHz); and the phase margin
should be greater than 45°.
If the bandwidth and phase margin are not within an
acceptable range, add R3 and C3 to slightly adjust the
crossover frequency and phase margin.
If the crossover frequency and phase margin still can't
meet the requirement after tuning R3 and C3, re-select
the ESR and COUT (mainly) or inductance value to change
the location of FLC and FESR then repeat step 4. Note that
the output voltage ripple and transient response should
still meet the specification after changing ESR, COUT or
L.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
Where TJ(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RP6104-01P Jan 2010
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet RP6104.PDF ] | |
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