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PDF RP6100 Data sheet ( Hoja de datos )
| Número de pieza | RP6100 | |
| Descripción | 5V to 12V Single Synchronous Buck PWM Controller | |
| Fabricantes | RICHPOWER | |
| Logotipo |  |
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Preliminary
RP6100
5V to 12V Single Synchronous Buck PWM Controller
General Description
The RP6100 series are single-phase synchronous buck
PWM DC-DC controllers designed to drive two
N-MOSFETs. They provide a highly accurate,
programmable output voltage precisely regulated to low
voltage requirement with an internal 0.8V reference.
The RP6100 series use a single feedback loop voltage
mode PWM control for fast transient response. The high
driving capability makes it suitable for large output current
applications. An oscillator with fixed frequency 200kHz
reduces the component size of the external inductor and
capacitor for saving PCB board area and cost.
The RP6100 series integrate complete protection functions
such as OCP, OVP and OTP UVP into SOP-8 (Exposed
Pad) surface mount package.
Ordering Information
RP6100
Package Type
SP : SOP-8 (Exposed Pad-Option 1)
Operating Temperature Range
G : Green (Halogen Free with Commer-
cial Standard)
Frequency / VREF Options / Soft Start-Time
D : 200k / 0.8V / 4ms
E : 200k / 0.8V / 9ms
Note :
Richpower Green products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Features
Single IC Supply Voltage ( 5V to 12V)
Drive Two N-MOSFETs
Fixed Operating Frequency at 200kHz
Voltage Mode PWM Control with External
Feedback Loop Compensation
Over Current Protection by Sensing MOSFET RDS(ON)
Hardware Pin for On/Off Control
Full 0 to 90% Duty Cycle
Fast Transient Response
RoHS Compliant and Halogen Free
Applications
Mother Boards and Desktop Servers
Graphic Cards
Switching Power Supply
Generic DC/DC Power Regulator
Pin Configurations
(TOP VIEW)
BOOT
UGATE
GND
LGATE/OCSET
8
27
GND
36
9
45
PHASE
COMP/SD
FB
VCC
SOP-8 (Exposed Pad)
RP6100-04P Jan 2011
1
1 page  
Preliminary
RP6100
Parameter
Oscillator
PWM
Frequenc y
RP6100D
RP6100E
Ramp Amplitude
Reference
Symbol
FSW
∆VOSC
Conditions
Min Typ Max Unit
170 200 230
kHz
170 200 230
-- 1.5 -- VP-P
Reference
Voltage
RP6100D
RP6100E
VREF
0.792 0.8 0.808
0.792 0.8 0.808
V
PWM Controller
Open Loop DC Gain
Gain Bandwidth
AO
GBW
-- 88 -- dB
-- 15 -- MHz
Maximum Duty
DMAX
fOSC = 200kHz
-- 92 -- %
PWM Controller Gate Driver
Upper Gate Source
Upper Gate Sink
Lower Gate Source
Lower Gate Sink
Protection
IUGATEsr
RUGATEsk
ILGATEsr
RLGATEsk
VBOOT − VPHASE = 12V
VUGATE − VPHASE = 0.1V, I = 50mA
VCC = 12V
VLGATE = 0.1V, I = 50mA
1
--
1
--
1.2
2.25
1.2
1
--
4
--
2
A
Ω
A
Ω
Under Voltage Protection (UVP)
Over Voltage Protection
Over Voltage Protection
LGATE OC Setting Current
Over Temperature Protection
Soft-Start
Interval
RP6100D
RP6100E
VFB_UVP
VFB_OVP
Vpre_ OV P
IOC SE T
TOTP
Sweep VFB
Sweep VFB (After POR)
Sweep VFB (Before POR)
TSS Measure FB from 10% to 90%
68 75 82 %
115 125 130 %
-- 130 --
%
22 25 28 µA
-- 165 --
°C
14
5.5 9
7
ms
--
COMP/SD Shutdown Threshold VSD
-- -- 0.2 V
Note 1. Stresses beyond those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution is recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity test board (4 Layers, 2S2P)
of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for SOP-8 (Exposed Pad)
package.
RP6100-04P Jan 2011
5
5 Page 
Preliminary
RP6100
out of the capacitor results in ripple voltage, which can be
determined using the following equation.
∆VOUT_ESR = ∆IL x ESR
In addition, the output voltage ripple is also influenced by
the switching frequency and the capacitance value.
∆VOUT_C
=
∆IL
×
8
×
1
COUT
× FSW
The total output voltage ripple is the sum of VOUT_ESR and
VOUT_C.
If the specification for steady-state output voltage ripple is
known, the ESR can be determined using the above
equations.
Another parameter that has influence on the output voltage
undershoot is the equivalent series inductance (ESL). The
rapid change in load current results in di/dt during transient.
Therefore, ESL contributes to part of the voltage
undershoot. Use capacitor that has low ESL to obtain better
transient performance. Generally, use several capacitors
connected in parallel can have better transient performance
than use single capacitor for the same total ESR.
Unlike the electrolytic capacitor, the ceramic capacitor has
relatively low ESR and can reduce the voltage deviation
during load transient. However, the ceramic capacitor can
only provide low capacitance value. Therefore, use a mixed
combination of electrolytic capacitor and ceramic capacitor
can also have better transient performance.
Feedback Loop Compensation
Figure 3 shows the voltage mode control loop for a buck
converter. The control loop consists of the modulator, output
LC filter and the compensator. The modulator is composed
of the PWM comparator and power MOSFETs. The PWM
comparator compares the error amplifier EA output (COMP)
with the oscillator (OSC) sawtooth wave to generate a PWM
signal. The MOSFETs is then switched on and off
according to the duty cycle of the PWM signal. The voltage
presented at PHASE node is a square wave of 0V to Vin.
The PHASE voltage is filtered by the output filter LOUT and
COUT to produce output voltage VOUT, which is fedback to
the inverting input of the error amplifier. The output voltage
is then regulated according to the reference voltage VREF.
In order to achieve fast transient response and accurate
output regulation, an adequate compensator design is
necessary. The goal of the compensation network is to
provide adequate phase margin (greater than 45 degrees)
and the highest 0dB crossing frequency. It is also
recommended to manipulate loop frequency response that
its gain crosses over 0dB at a slope of −20dB/dec.
OSC
PWM
Comparator
∆VOSC
-
+
Driver
VIN
Driver
LOUT
PHASE
COUT
VOUT
ZFB
COMP
-
EA+
REF
ZIN
ESR
C2 ZFB
C1 R2
C3
ZIN VOUT
R3
COMP
- FB
EA+
REF
R1
Figure 3. Control Loop for Voltage Mode Buck Converter
1) Modulator and Output LC filter
Referring to Figure 3, the modulator gain is the input voltage
VIN divided by the peak to peak oscillator voltage VOSC as
shown as following Equation :
ModulatorGain
=
VIN
∆VOSC
where ∆VOSC = 1.5V (typ.)
The output LC filter introduces a double pole to the transfer
function, creating −40dB/decade gain slope above its corner
frequency, with a phase lag of 180 degrees. The frequency
at the double-pole of LC filter is expressed as follows.
fLC =
1
2π × LOUT × COUT
RP6100-04P Jan 2011
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet RP6100.PDF ] | |
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