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PDF WM9082 Data sheet ( Hoja de datos )
| Número de pieza | WM9082 | |
| Descripción | PDM Input Mono 3W Class D Speaker Driver | |
| Fabricantes | Wolfson Microelectronics | |
| Logotipo |  |
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WM9082
PDM Input Mono 3W Class D Speaker Driver
DESCRIPTION
The WM9082 is a high-performance sigma-delta Class D
speaker driver. Audio input is supported using a stereo PDM
interface; clock and control-code detection circuitry supports
all of the audio and control functions via a 2-wire interface.
The digital audio interface provides excellent noise
immunity, eliminating traditional input-filtering components.
The flexible 2-wire interface minimises the PCB footprint and
simplifies software development.
The combined audio and control interface configuration is
ideal for enabling the WM9082 to be located close to the
speaker; this reduces the length of the output connections,
giving good EMC performance and removing the need for
output filter components.
The sigma-delta architecture provides good power efficiency
and improved EMI performance with respect to traditional
PWM Class D designs.
A first-order high-pass filter can be selected on the input
signal to remove DC offsets and help to prevent speaker
damage. Other features include a low-power mute state,
and output slew-rate control.
Short-circuit and thermal protection is provided.
The WM9082 is supplied in a 9-ball 1.56 x 1.46mm CSP
package, with 0.5mm ball pitch.
FEATURES
Sigma-Delta Class-D speaker driver
- 92dB SNR - ‘A’ weighted
- 2.5W into 4 (5V supply, 1% THD)
- 1.3W into 4 (3.6V supply, 1% THD)
- 1.25W into 8 (5V supply, 1% THD)
- 650mW into 8 (3.6V supply, 1% THD
Stereo PDM digital audio input
Supports 32kHz, 44.1kHz, 48kHz sample rates (128fs input)
Automatic Left/Right channel selection
First-order high pass filter (HPF)
RF noise suppression
Pop and click suppression
Programmable output slew rates for low EMI
Short-circuit and thermal protection
9-ball CSP package
APPLICATIONS
Mobile Handsets
Portable Media Players (PMP)
Notebooks / Laptop computers
LCD televisions
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
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Production Data, August 2012, Rev 4.1
Copyright 2012 Wolfson Microelectronics plc
1 page  
Production Data
WM9082
ELECTRICAL CHARACTERISTICS
Test Conditions
SPKVDD = 3.6V, DVDD = 1.8V, SPKGND=GND = 0V, TA = +25oC, Load = 4Ω+33µH,
1kHz signal, CLK=6.144MHz (128fs), fs=48kHz unless otherwise stated.
PARAMETER
Speaker Driver
Signal to Noise ratio
Idle channel noise
Total Harmonic
Distortion + Noise
Output Power
(THD+N = 1%)
SYMBOL
SNR
THD+N
PO
Speaker Load resistance
(see note 1)
Speaker Load
capacitance
(see note 1)
PSRR (SPKVDD)
PSRR
Power efficiency
Clocking (IN1 or IN2)
CLK input
Digital Input (IN1 or IN2)
Input high level
(see note 1)
Input low level
(see note 1)
Input capacitance
(see note 1)
Input leakage
Other Parameters
Pop-free start-up time
Shutdown time
TEST CONDITIONS
A-weighted
A-weighted
PO = 625mW
RL = 4, SPKVDD = 3.6V
RL = 4, SPKVDD = 5.0V
RL = 8, SPKVDD = 3.6V
RL = 8, SPKVDD = 5.0V
Direct connection to
SPKOUTP+SPKOUTN
200mV (peak-peak) 217Hz
Idle digital audio input while in
the ON state
RL = 4, PO = 625mW,
SPKVDD = 3.6V
RL = 8, PO = 625mW,
SPKVDD = 3.6V
fs = 48kHz
fs = 44.1kHz
fs = 32kHz
‘OFF’ state to ‘ON’ state
(see Figure 3)
‘ON’ state to ‘OFF’ state
(see Figure 3)
MIN
3
0.7 x DVDD
-0.9
TYP
92
66
-70
1.3
2.5
0.65
1.25
70
82
86
6.144
5.6448
4.096
1
1
MAX
200
0.3 x DVDD
10
0.9
UNIT
dB
VRMS
dB
W
pF
dB
%
MHz
V
V
pF
A
ms
ms
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PD, August 2012, Rev 4.1
5
5 Page 
Production Data
ID FUNCTION
DESCRIPTION
Code 1
Start Up (3.6V SPKVDD)
Code 2
Standby
Code 3
EMI control 1
Code 4
32kHz mode control
Code 5
High Pass Filter control
Code 6
Page 2 access
Code 7
Reserved
Code 8
Reserved
Code 9
Start Up (3.6V SPKVDD)
Code 10
Start Up (5.0V SPKVDD)
Table 2 WM9082 Page 1 Control Codes
Fast Start-Up for default SPKVDD
Disable Class D output
Invert SR[1]
Select 32kHz sample rate mode
Disable 2Hz High Pass Filter
Enable Page 2 Control Codes
Start-Up for SPKVDD = 3.6V
Start-Up for SPKVDD = 5.0V
WM9082
CONTROL
CODE
AA
66
F0
8B
39
56
D1
D2
D4
D8
ID FUNCTION
DESCRIPTION
Code 1
Reserved
Code 2
Reserved
Code 3
Performance control 1
Code 4
Reserved
Code 5
Reserved
Code 6
Reserved
Code 7
Reserved
Code 8
Reserved
Code 9
EMI control 2
Code 10
Performance control 2
Table 3 WM9082 Page 2 Control Codes
Invert PC1[0]
Invert SR[0]
Increment PC2[1:0]
CONTROL
CODE
AA
66
F0
8B
39
56
D1
D2
D4
D8
The output driver slew-rate control is configurable using the SR[1] and SR[0] bits. These fields are
defined in Table 4. The slew-rate Control Code sequences are described in Table 6.
SR[1]
SR[0]
00
01
10
11
Table 4 Output Slew Rate Control bits
OUTPUT SLEW RATE
(OUTPUT RISE / FALL TIME)
5ns (Default)
10ns
20ns
40ns
The output driver operating mode is configurable using the PC1[0] and PC2[1:0] bits. These fields are
defined in Table 5. Selected operating mode Control Code sequences are described in Table 6.
PC1[0]
PC2[1:0]
1 00
1 01
1 10
1 11
0 XX
Table 5 Operating Mode Control bits
Best PSRR
↑
↑
↑
DESCRIPTION
↓
↓
↓
Best SNR
(default)
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PD, August 2012, Rev 4.1
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet WM9082.PDF ] | |
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