PDF CS53L30 Data sheet ( Hoja de datos )

Número de pieza	CS53L30
Descripción	Low-Power Quad-Channel Microphone ADC
Fabricantes	Cirrus Logic
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No Preview Available ! CS53L30 Low-Power Quad-Channel Microphone ADC with TDM Output Analog Input and ADC Features System Features  91-dB dynamic range (A-weighted) @ 0-dB gain  –84-dB THD+N @ 0-dB gain  Four fully differential inputs: Four analog mic/line inputs  Four analog programmable gain amplifiers  –6 to +12 dB, in 0.5-dB steps  +10 or +20 dB boost for mic input  Four mic bias generators  MUTE pin for quick mic mute and programmable quick power down Digital Processing Features  Volume control, mute, programmable high-pass filter, noise gate  Two digital mic (DMIC) interfaces Digital Output Features  Two DMIC SCLK generators  Four-channel I2S output or TDM output. Four CS53L30s can be used to output 16 channels of 24-bit 16-kHz sample rate data on a single TDM line.  Native (no PLL required) support for 6-/12-MHz, 6.144-/ 12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz master clock rates and 8- to 48-kHz audio sample rates  Master or Slave Mode. Clock dividers can be used to generate common audio clocks from single-master clock input.  Low power consumption  Less than 4.5-mW stereo (16 kHz) analog mic record  Less than 2.5-mW mono (8 kHz) analog mic record  Selectable mic bias and digital interface logic voltages  High-speed (400-kHz) I²C control port  Available in 30-ball WLCSP and 32-pin QFN Applications  Voice-recognition systems  Advanced headsets and telephony systems  Voice recorders  Digital cameras and video cameras IN1+/DMIC1_SD IN1– IN2+ IN2– IN3+/DMIC2_SD IN3– IN4+ IN4– MIC 1_BIAS MIC 2_BIAS MIC3_BIAS MIC4_BIAS VA LDO VD + – + – +10 or +20 dB + ADC1A – + ADC1B – –6 to +12 dB, 0.5 dB steps MCLK_INT CS53L30 Digital Processing HPF, Noise Gate, Volume, Mute 2 + – + – +10 or +20 dB + – ADC2A + – ADC2B –6 to +12 dB, 0.5 dB steps MCLK_INT MIC1 Bias MIC2 Bias MIC3 Bias MIC4 Bias DMIC HPF, Noise Gate, Volume, Mute 2 Control Port MCLK_INT Clock Divider Synchronizer Level Shifters 4 Synchronous SRC Audio Serial Port RESET DMIC1_SCLK Control SYNC MCLK Serial Port VP DMIC2_SCLK Port MUTE http://www.cirrus.com Copyright  Cirrus Logic, Inc. 2013–2015 (All Rights Reserved) DS992F2 MAR '15 1 page 1.2 QFN CS53L30 1.2 QFN 32 31 30 29 28 27 26 25 IN2+ 1 IN2– 2 IN3+/DMIC2_SD 3 IN3– 4 IN4+ 5 IN4– 6 VA 7 GNDA 8 Thermal Pad 24 SCL 23 ASP_SDOUT2/AD0 22 ASP_LRCK/FSYNC 21 VA 20 GNDD 19 SYNC 18 RESET 17 INT 9 10 11 12 13 14 15 16 Figure 1-2. Top-Down (Through-Package) View—32-Pin QFN Package 1.3 Pin Descriptions Name Ball Pin ## Power Supply I/O Table 1-1. Pin Descriptions Description Internal Connection Capture-Path Pins IN1+/DMIC1_SD A1 31 VA I Noninverting Inputs/DMIC Inputs. Programmable IN2+ A2 1 Positive analog inputs for the stereo IN3+/DMIC2_SD A3 3 IN4+ A4 5 ADCs when CH_TYPE = 0 (default) or DMIC inputs when CH_TYPE = 1. IN1– IN2– IN3– IN4– B1 32 VA I Inverting Inputs. Negative analog inputs Programmable B2 2 for the stereo ADCs when CH_TYPE = 0 B3 4 B4 6 (default) or unused when CH_TYPE = 1. Driver — — Receiver State at Reset Hysteresis on CMOS input Hysteresis on CMOS input — — DS992F2 5 5 Page CS53L30 3 Characteristics and Specifications Table 3-6. MIC BIAS Characteristics Test conditions (unless otherwise specified): Fig. 2-1 shows CS53L30 connections; GNDA = GNDD = 0; all voltages are with respect to ground; VA = 1.8 V, VP = 3.6 V, TA = +25°C; only one bias output is powered up at a time; MCLK_INT_SCALE = 0. Parameters Min Typ Max Units Output voltage 1 MIC_BIAS_CTRL = 01 (1.8-V mode) MIC_BIAS_CTRL = 10 (2.7-V mode) 1.71 2.61 1.80 2.75 1.89 V 2.86 V Mic bias startup delay 2 — 10 — ms Rise time 3 DC output current (IOUT) Integrated output noise IOUT = 500 µA, MIC_BIAS_CTRL = 01 (1.8-V mode) — 0.2 — ms IOUT = 500 µA, MIC_BIAS_CTRL = 10 (2.7-V mode) — 0.5 — ms IOUT = 2 mA — — 3 ms Per output — — 2 mA f = 100 Hz–20 kHz — 3 — µVrms Dropout voltage 4 — — 340 mV PSRR reduction voltage 5 — — 500 mV Output resistance (ROUT) IOUT = 2-mA — 30 — 1.The output voltage includes attenuation due to the MIC BIAS output resistance (ROUT). 2.Startup delay times are approximate and vary with MCLKINT frequency. If MCLK_INT_SCALE = 1, the startup delay time is scaled up by the MCLKINT scaling factor. The MCLKINT scaling factor is 1, 2, or 4, depending on FsEXT. See Table 4-2. 3.From 10% to 90% of typical output voltage. External capacitor on MICx_BIAS is as shown in Fig. 2-1. 4.Dropout voltage indicates the point where an output’s voltage starts to vary significantly with reductions to its supply voltage. When the VP supply voltage drops below the programmed MICx_BIAS output voltage plus the dropout voltage, the MICx_BIAS output voltage progressively decreases as its supply decreases. Dropout voltage is measured by reducing the VP supply until MICx_BIAS drops 10 mV from its initial voltage with the default typical test condition VP voltage (= 3.6 V, as in test conditions listed above). The difference between the VP supply voltage and the MICx_BIAS voltage at this point is the dropout voltage. For instance, if the initial MICx_BIAS output is 2.86 V when VP = 3.6 V and VP = 3.19 V when MICx_BIAS drops to 2.85 V (–10 mV), the dropout voltage is 340 mV (3.19 V – 2.85 V). 5.PSRR voltage indicates the point where an output’s supply PSRR starts to degrade significantly with supply voltage reductions. When the VP supply voltage drops below the programmed MICx_BIAS output voltage plus the PSRR reduction voltage, the MICx_BIAS output’s PSRR progressively decreases as its supply decreases. PSRR reduction voltage is measured by reducing the VP supply until MICx_BIAS PSRR @ 217 Hz falls below 100 dB. The difference between the VP supply voltage and the MICx_BIAS voltage at this point is the PSRR reduction voltage. For instance, if the MICx_BIAS PSRR falls to 99.9 dB when VP is reduced to 3.25 V and the MICx_BIAS output voltage is 2.75 V at that point, PSRR reduction voltage is 500 mV (3.25 V – 2.75 V). Table 3-7. Power-Supply Rejection Ratio (PSRR) Characteristics Test conditions (unless specified otherwise): Fig. 2-1 shows CS53L30 connections; input test signal held low (all zero data); GNDA = GNDD = 0; voltages are with respect to ground; VA = 1.8 V, VP = 3.6 V; TA = +25°C. Parameters 1 Min Typical Max Units INx (32-dB analog gain) PSRR with 100-mVpp signal AC coupled to VA supply 217 Hz — 70 — dB 1 kHz — 70 — dB 20 kHz — 55 — dB MICx_BIAS (MICx_BIAS = 2.7-V mode, IOUT = 500 µA) PSRR with 100 mVpp signal AC coupled to VA supply VP_MIN = 0 (3.0 V) 217 Hz — 105 — dB 1 kHz — 100 — dB 20 kHz — 95 — dB MICx_BIAS (MICx_BIAS = 2.7-V mode, IOUT = 500 µA) PSRR with 100 mVpp signal AC coupled to VA supply VP_MIN = 1 (3.2 V) 217 Hz — 105 — dB 1 kHz — 100 — dB 20 kHz — 95 — dB MICx_BIAS (MICx_BIAS = 2.7-V mode, IOUT = 500 µA) PSRR with 100 mVpp signal AC coupled to VP supply VP_MIN = 0 (3.0 V) 217 Hz — 90 — dB 1 kHz — 90 — dB 20 kHz — 70 — dB MICx_BIAS (MICx_BIAS = 2.7-V mode, IOUT = 500 µA) PSRR with 1 Vpp signal AC coupled to VP supply VP_MIN = 1 (3.2 V) 217 Hz — 120 — dB 1 kHz — 115 — dB 20 kHz — 105 — dB 1.PSRR test configuration: Typical PSRR can vary by approximately 6 dB below the indicated values. Analog Output PSRR +5V Power DAC OUT GND + 5V – + Operational Amplifier DUT PWR GND OUT Digital Output PSRR +5V Power DAC OUT GND + 5V – + Operational Amplifier DUT PWR GND SDOUT OUT Analog Test Equipment Analog Generator –+ – + Analog Analyzer OUT Test Equipment –+ Analog Generator Analog Analyzer Digital Analyzer DS992F2 11 11 Page

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