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PDF LS7212N Data sheet ( Hoja de datos )
| Número de pieza | LS7212N | |
| Descripción | PROGRAMMABLE DIGITAL DELAY TIMER | |
| Fabricantes | LSI | |
| Logotipo |  |
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LSI/CSI
LS7211N-7212N
U® L LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
A3800
PROGRAMMABLE DIGITAL DELAY TIMER
July 2009
FEATURES:
• 8-bit programmable delay from microseconds to days
• On chip oscillator (RC or Crystal) or external clock time base
• Selectable prescaler for real time delay generation based
on 50Hz/60Hz time base or 32,768Hz watch crystal
• Four operating modes
• Reset input for delay abort
• Low quiescent and operating current
• Direct relay drive
• +3V to +18V operation (VDD - VSS)
• LS7211N, LS7212N (DIP); LS7211N-S, LS7212N-S (SOIC)
- See Figure 1 -
DESCRIPTION:
The LS7211N and LS7212N are CMOS integrated circuits for
generating digitally programmable delays. The delay is con-
trolled by 8 binary weighted inputs, WB0 - WB7, in conjunction
with an applied clock or oscillator frequency. The programmed
time delay manifests itself in the Delay Output (OUT) as a func-
tion of the Operating Mode selected by the Mode Select inputs
A and B: One-Shot, Delayed Operate, Delayed Release or Dual
Delay. The time delay is initiated by a transition of the Trigger
Input (TRIG).
PIN ASSIGNMENT - TOP VIEW
A1
B
V DD (+V)
2
3
RC/CLOCK 4
RCS/CLKS
PSCLS
5
6
RESET 7
V SS (-V)
OUT
8
9
18 TRIG
17 WB0
16 WB1
15 WB2
14 WB3
13 WB4
12 WB5
11 WB6
10 WB7
A1
B2
18 TRIG
17 WB0
I/O DESCRIPTION:
MODE SELECT Inputs A & B (Pins 1 & 2)
The 4 operating modes are selected by Inputs A and B
according to Table 1
V DD (+V) 3
XTLI/CLOCK
XTLO
4
5
16 WB1
15 WB2
14 WB3
TABLE 1. MODE SELECTION
A B MODE
0 0 One-Shot (OS)
0 1 Delayed Operate (DO)
1 0 Delayed Release (DR)
1 1 Dual Delay (DD)
PSCLS 6
RESET 7
V SS (-V) 8
OUT 9
FIGURE 1
13 WB4
12 WB5
11 WB6
10 WB7
Each input has an internal pull-up resistor of about 500kΩ.
One-Shot Mode (OS)
A positive transition at the TRIG input causes OUT to switch
low without delay and starts the delay timer. At the end of the
programmed delay timeout, OUT switches high. If a delay time-
out is in progress when a positive transition occurs at the TRIG
input, the delay timer will be restarted. A negative transition at
the TRIG input has no effect.
Delayed Operate Mode (DO)
A positive transition at the TRIG input starts the delay timer. At
the end of the delay timeout, OUT switches low. A negative
transition at the TRIG input causes OUT to switch high without
delay. OUT is high when TRIG is low.
7211N-07209-1
Delayed Release Mode (DR)
A negative transition at the TRIG input starts the delay tim-
er. At the end of the delay timeout, OUT switches high. A
postive transition at the TRIG input causes OUT to switch
low without delay. OUT is low when TRIG is high.
Dual Delay Mode (DD)
A positive or negative transition at the TRIG input starts
the delay timer. At the end of the delay timeout, OUT
switches to the logic state which is the inverse of the TRIG
input. If a delay timeout is in progress when a transition
occurs at the TRIG input, the delay timer is restarted.
1 page  
Clock
TRIG
A, B
WB0-WB7
OUT
t0
t3
t1
t2
A = 0, B = 1, Delayed Operate
Programmed Delay
t1
t4
Immediate Release
Note 1. TRIG input is clocked in by the negative edge of external clock.
Note 2. Inputs A, B and WB0 - WB7 are sampled only at a TRIG input transition and ignored at all other times.
Note 3. OUT is switched by the positive edge of the external clock.
FIGURE 3. INPUT/OUTPUT TIMING
TRIG
RESET
OUT(OS)
OUT(DO)
OUT(DR)
OUT(DD)
AB
C
D
E
F
GH
A. Turn-on delay in DO and DD modes; Pulse-width in OS mode.
B. Turn-off delay in DR and DD modes.
C. Pulse-width extended by re-trigger in OS mode.
No effect in DO and DD modes because TRIG switches back low before turn-on delay has timed out.
D. Turn-off delay in DR mode.
E. Turn-on delay in DO and DD modes; pulse-width in OS mode.
F. No effect in DO, DR and DD modes because of TRIG’s switching back to opposite levels.
G. Time-outs aborted and OUT forces high by RESET.
H. After the removal of RESET, OUT switches to the inverse polarity of TRIG
immediately (DR) or after the timeout (DO, DD). No effect in OS.
FIGURE 4. MODE ILLUSTRATION WITH TRIG, OUT AND RESET
7211N-061906-5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet LS7212N.PDF ] | |
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