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PDF LS7267 Data sheet ( Hoja de datos )
| Número de pieza | LS7267 | |
| Descripción | 24-BIT DUAL-AXIS QUADRATURE COUNTER | |
| Fabricantes | LSI | |
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LSI/CSI
LS7267
U® L LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
A3800
24-BIT DUAL-AXIS QUADRATURE COUNTER
OCT 2015
FEATURES:
• Up to 50MHz count frequency in non-quadrature mode;
Up to 5.6MHz clock frequency (22 x 106 counts/sec) in
x4 quadrature mode.
• Dual 24-bit counters to support X and Y axes in
motion control applications. • Dual 24-bit comparators.
• Digital filtering of the input quadrature clocks
• Programmable 8-bit separate filter clock prescalers
for each axis.
• Error flags for noise exceeding filter band width.
• Programmable Index Input and other programmable I/Os.
• Independent mode programmability for each axis.
• Programmable count modes:
Quadrature (x1, x2, x4) / Non-quadrature,
Normal / Modulo-N / Range Limit / Non-Recycle,
Binary / BCD.
• 8-bit 3-State data I/O bus.
• 3V to 5.5V operation (VDD - VSS).
• TTL/CMOS compatible I/Os.
• LS7267 (DIP); LS7267-S (SOIC); LS7267-TS (TSSOP)
PIN ASSIGNMENT
TOP VIEW
YLCNTR/YLOL 1
FCK 2
V DD (+5V) 3
D0 4
D1 5
D2 6
D3 7
D4 8
D5 9
D6 10
D7 11
V SS (GND ) 12
C/D 13
WR 14
28 YRCNTR/YABG
27 YFLG1
26 YFLG2
25 YA
24 YB
23 XFLG2
22 XFLG1
21 XB
20 XA
19 XLCNTR/XLOL
18 XRCNTR/XABG
17 X/Y
16 RD
15 CS
LS7267 Registers:
LS7267 has a set of registers associated with each X and Y axis. All X-axis registers have the name prefix X,
whereas all Y-axis registers have the prefix Y. Selection of a specific register for Read/Write is made from the decode
of the three most significant bits (D7 - D5) of the data-bus. CS input enables the IC for Read/Write. C/D input selects
between control and data information for Read/Write. Following is a complete list of LS7267 registers.
Preset Registers: XPR and YPR
Each of these PRs are 24-bit wide. 24-bit data can be written into a PR, one byte at a time, in a sequence of three data
write cycles.
PR
7 07 07 0
HI BYTE
(PR2)
MID BYTE
(PR1)
LO BYTE
(PR0)
Counters: XCNTR and YCNTR
Each of these CNTRs are 24-bit synchronous Up/Down counters. The count clocks for each CNTR is derived from its
associated A/B inputs. Each CNTR can be loaded with the content of its associated PR.
Output Latches: XOL and YOL
Each OL is 24-bits wide. In effect, the OLs are the output ports for the CNTRs. Data from each CNTR can be loaded
into its associated OL and then read back on the data-bus, one byte at a time, in a sequence of three data Read
cycles.
OL
7 07 0 7 0
HI BYTE
(OL2)
MID BYTE
(OL1)
LO BYTE
(OL0)
Byte Pointers: XBP and YBP
The Read and Write operations on an OL or a PR always accesses one byte at a time. The byte that is accessed is
addressed by one of the BPs. At the end of every data Read or Write cycle on an OL or a PR, the associated BP is
automatically incremented to address the next byte.
7267-102215-1
1 page  
I/O pins:
Following is a description of all the input/output pins.
YLCNTR/YLOL/ (pin 1). Input. Programmable input in
the y-axis which can be configured with the YIOR
register to function as either LD_YCNTR or LD_YOL
input. LD_YCNTR causes the YPR to be loaded into
YCNTR when the input is at active level. LD_YOL
causes YCNTR to be loaded into YOL when the input is
at active level.
In quadrature mode the input can further be initialized
with the YIDR register to function in either INDEX mode
or non-INDEX mode. The INDEX mode allows for the
direct interface with the INDEX output of an incremental
encoder. In this mode the YLCNTR/YLOL/ input is
sampled with the filter clock derived from the FCK input
clock which is used for validating the quadrature clocks
as well
In the INDEX mode the YCLNTR/YLOL/ input can be
configured for either high or low active logic levels with
the YIDR. In the non-INDEX mode the active level is not
programmable and is unconditionally set to low active.
In the non-INDEX mode YCLNTR/YLOL/ input is not
sampled with the filter clock and can be applied
asynchronously with respect to YA and YB inputs. In
non-quadrature mode the YCLNTR/YLOL/ input is
unconditionally set to the non-INDEX mode.
FCK. (pin 2). Input. A clock applied at the FCK input is
used for generating filter clocks for both X and Y axes.
The filter clocks are used for validating the quadrature
clocks (at XA, XB, YA and YB inputs), and the INDEX
signal ( at XLCNTR/XLOL/ or XRCNTR/ or
YLCNTR/YLOL/ or YRCNTR in INDEX mode). The clock
at the FCK input is divided down separately by XPSC
and YPSC prescalers to generate the filter clock for each
axis. The prescaler output frequency is given by:
fFCKn = fFCK/(n+1), where fFCK is the frequency at the FCK
input and n = [XPSC] or [YPSC].
For proper operation in the quadrature mode the
following condition of frequencies must be satisfied:
fFCKn ≥ 8fQAB, where fQAB is the clock frequency at XA or
XB or YA or YB input..
In non-quadrature mode the filter clock is not used and
the FCK input must be tied off to either VDD or VSS.
VDD (pin 3). Supply voltage positive rail. +3V to +5V.
D0 through D7 (pins 4 through 11). Inputs/Outputs. The
8-bit databus D0 through D7 is a 3-state portal for the
READ/WRITE operation in and of the device. The
databus is common to both axes. During a read
operation when both CS/ and RD/ inputs are low, the
content of either the OL or the FLAG register of the
selected axis is placed on databus. During a write
operation the content of the databus is written into the
selected register at the trailing edge of the WR/ pulse.
7267-091615-5
When CS/ is high the databus is disabled and placed in
the high impedance state.
VSS (pin 12). Supply voltage negative rail or GND.
D/C (pin 13). Input. This input selects between a control
register or a data register for read/write operation
according to Table 1. When low, a write operation
causes the content of the databus to be written into the
selected PR register. When high, a write causes the
databus to be written into the selected control register.
During a read operation, a low at the D/C input causes
the content of the selected OL to be output on the
databus while a high causes the content of the selected
FLAG register to be output on the databus.
WR/ (pin 14). Input. A low pulse at the WR/ input causes
the content of the databus to be written into the selected
register according to Table 1. The write operation is
completed at the trailing edge of the WR/ pulse.
CS/ (pin 15). Input. A low at the CS/ input enables the
device for read or write operations. When the CS/ input
is high the read and write operations are disabled and
the databus, D0-D7 is placed in the high impedance
state.
RD/ (pin 16). Input. A low at the RD/ input causes the
content of the selected register to be output on the
databus according to Table 1.
X/Y (pin 17). Input. Selects between X and Y axis for
read and write. A low at this input selects the X axis
while a high selects the Y axis.
XRCNTR/XABG (pin 18). Input. Programmable input in
the x-axis which can be configured with the XIOR
register to function as either R_XCNTR or E_XAB input.
R_XCNTR causes the XCNTR to be reset to 0 when the
input is in the active level. E_XAB causes the input to
function as the XA and XB enable/disable gate. In this
mode XA and XB become enabled when the
XRCNTR/XABG input is high and disabled when the
input is low,
In quadrature mode the input can further be initialized
with the XIDR register to function in either INDEX mode
or non-INDEX mode. In the INDEX mode the
XRCNTR/XABG is sampled with the filter clock derived
from the FCK input clock which is used for validating the
quadrature clocks as well.
When configured in the INDEX mode the
XRCNTR/XABG input must also be configured as
R_XCNTR to function correctly. In the INDEX mode the
XRCNTR/XABG input can be configured for either high
or low active logic levels for the R_XCNTR function via
the XIDR register. In the non-INDEX mode the active
level is not programmable and is unconditionally set to
low active for the R_XCNTR function.
In the non-INDEX mode XRCNTR/XABG input is not
sampled with the filter clock and can be applied
5 Page 
UP DOWN
A
tQ1
B
X4_CLK
X2_CLK
X1_CLK
CNTR advances
tQ2
Fig 4. A/B quadrature clocks and internal count clocks in X1, X2 and X4 modes
A
B
INDEX
UP
thi
tsi
DOWN
tidx
X4_CLK
CNTR
fffffd fffffe ffffff 0 1 2
3 2 1 0 ffffff fffffe fffffd
INDX (FLG1)
tQ3
CY/ (FLG1)
BW/ (FLG2)
CMP/ (FLG1
tQ3
tQ3
tQ3
Note. CMP/ signal is arbitrarily shown to be generated at CNTR = fffffe
Note. In modulo-N and range-limit modes the CMP/ output is generated in up count only
Note. INDEX signal must overlap quarter cycle of both A and B high or both A and B low. Shown here both low.
Fig 5. FLG1 and FLG2 outputs in quadrature count mode
7267-052815-11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet LS7267.PDF ] | |
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