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VS8053b fiches techniques PDF

VLSI - AUDIO PROCESSOR

Numéro de référence VS8053b
Description AUDIO PROCESSOR
Fabricant VLSI 
Logo VLSI 





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VS8053b fiche technique
VS8053b Datasheet
VS8053b - AUDIO PROCESSOR WITH
Ogg Vorbis / FLAC / WAV SUPPORT
Features
Description
Laser-fused version of VS1053b
Decodes
Ogg Vorbis;
FLAC with software plugin;
WAV (PCM + IMA ADPCM)
Encodes Ogg Vorbis w/ software plugin
Encodes stereo IMA ADPCM / PCM
Streaming support for WAV
Unique serial number for user code pro-
tection
EarSpeaker Spatial Processing
VS8053b is an audio processor with a high
performance stereo ADC and DAC. Each de-
vice has a factory-programmable unique chip
ID that provides a basis for digital rights man-
agement or unit identification features. VS8053b
supports audio formats that do not require
a license (Ogg Vorbis, PCM, IMA-ADPCM,
FLAC). By using the Ogg Vorbis encoder plu-
gin the device can be used to build a high per-
formance and low cost digital audio encoder-
decoder link.
Bass and treble controls
Operates with a single 12..13 MHz clock
VS8053b contains a high-performance, pro-
prietary low-power DSP processor core VS_DSP4,
Can also be used with a 24..26 MHz clock
Internal PLL clock multiplier
Low-power operation
High-quality on-chip stereo DAC with no
phase error between channels
Zero-cross detection for smooth volume
change
Stereo earphone driver capable of driv-
ing a 30 load
16 KiB instruction RAM and 16 KiB data RAM
for user applications running simultaneously
with built-in decoders, serial control and in-
put data interfaces, upto 8 general purpose
I/O pins, an UART, as well as a high-quality
variable-sample-rate stereo ADC (mic, line,
line + mic or 2×line) and stereo DAC, fol-
lowed by an earphone amplifier and a com-
mon voltage buffer.
Quiet power-on and power-off
VS8053b receives its input bitstream through
I2S output interface for external DAC
a serial input bus, which it listens to as a sys-
Separate voltages for analog, digital, I/O tem slave. The input stream is processed
On-chip RAM for user code and data
Serial control and data interfaces
Can be used as a slave co-processor
SPI flash boot for special applications
and passed through a asynchronous sample
rate converter and digital volume control to
an 18-bit oversampling, multi-bit, sigma-delta
DAC.
I2S
UART for debugging purposes
RCAP
New functions may be added with soft- LINE1
ware and upto 8 GPIO pins
Lead-free RoHS-compliant package
LINE2/
MICP
MICN
MUX
MIC
amplifier
Stereo
ADC
Stereo
DAC
Stereo Earphone
Driver
X ROM
LEFT
GBUF
RIGHT
DREQ
SO
SI
SCLK
XCS
XDCS
Serial
Data/
Conrol
Interface
VSDSP4
Processor
X RAM
Y ROM
TX
RX
OSCI
OSCO
XRESET
TEST
UART
Clock
Instruction
ROM
Instruction
RAM
Y RAM
GPIO
8
GPIO
Version: 1.22, 2014-12-19
1

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