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PDF IDT7140LA Data sheet ( Hoja de datos )
| Número de pieza | IDT7140LA | |
| Descripción | HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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HIGH SPEED
1K X 8 DUAL-PORT
STATIC SRAM
IDT7130SA/LA
IDT7140SA/LA
Features
◆ High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25/55/100ns (max.)
– Military: 25/35/55/100ns (max.)
◆ Low-power operation
– IDT7130/IDT7140SA
— Active: 550mW (typ.)
— Standby: 5mW (typ.)
– IDT7130/IDT7140LA
— Active: 550mW (typ.)
— Standby: 1mW (typ.)
◆ MASTER IDT7130 easily expands data bus width to 16-or-
more-bits using SLAVE IDT7140
◆ On-chip port arbitration logic (IDT7130 Only)
◆ BUSY output flag on IDT7130; BUSY input on IDT7140
◆ INT flag for port-to-port communication
◆ Fully asynchronous operation from either port
◆ Battery backup operation–2V data retention (LA only)
◆ TTL-compatible, single 5V ±10% power supply
◆ Military product compliant to MIL-PRF-38535 QML
◆ Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆ Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin
PLCC, and 64-pin STQFP and TQFP
◆ Green parts available, see ordering information
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL(1,2)
A9L
A0L
I/O
Control
I/O
Control
Address
Decoder
CEL
OEL
R/WL
10
MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
10
CER
OER
R/WR
INTL(2)
NOTES:
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.
IDT7140 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor.
©2016 Integrated Device Technology, Inc.
1
,
I/O0R-I/O7R
BUSYR(1,2)
A9R
A0R
INTR(2)
2689 drw 01
MAY 2016
DSC-2689/16
1 page  
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Pin Configurations(1,2,3) (con't.)
Military, Industrial and Commercial Temperature Ranges
N/C
N/C
N/C
INTR
BUSYR
R/WR
CER
VCC
VCC
CEL
R/WL
BUSYL
INTL
N/C
N/C
N/C
48 47 46 4544 43 42 4140 39 383736 35 3433
49 32
50 31
51 30
52 29
53 28
54 27
55 7130/40
56 PP64 & PN64(4)
57
26
25
24
58 23
59 22
60 21
61 20
62 19
63 18
64 17
1 2 3 4 5 6 7 8 9 10 11 1213 14 1516
I/O5R
I/O4R
N/C
I/O3R
I/O2R
I/O1R
I/O0R
GND
GND
N/C
I/O7L
I/O6L
I/O5L
I/O4L
N/C
I/O3L
2689 drw 05
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PP64 package body is approximately 10 mm x 10 mm x 1.4mm.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. Thispackagecodeisusedtoreferencethepackagediagram
5
5 Page 
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
BUSYOUT
PREVIOUS DATA VALID
DATA VALID
tBDDH (2,3)
2689 drw 08
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same the address location. For simultaneous read operations,
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 2, Either Side(3)
CE
OE
DATAOUT
ICC
CURRENT
ISS
tACE
tAOE (4)
tLZ (1)
tLZ (1)
tPU
50%
tHZ (2)
tHZ (2)
VALID DATA
tPD(4)
50%
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. R/W = VIH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
2689 drw 09
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet IDT7140LA.PDF ] | |
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