PDF ATmega16HVA Data sheet ( Hoja de datos )

Número de pieza	ATmega16HVA
Descripción	Microcontroller
Fabricantes	ATMEL Corporation
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Features • High Performance, Low Power AVR® 8-bit Microcontroller • Advanced RISC Architecture – 131 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 4 MIPS Throughput at 4 MHz • High Endurance Non-volatile Memorie segments – 8K/16K Bytes of In-System Self-Programmable Flash Program Memory(ATmega8HVA/16HVA) – 256 Bytes EEPROM – 512 Bytes Internal SRAM – Write/Erase cycles: 10,000 Flash/100,000 EEPROM – Data Retention: 20 years at 85°C /100 years at 25°C(1) – Programming Lock for Software Security • Battery Management Features – One or Two Cells in Series – Over-current Protection (Charge and Discharge) – Short-circuit Protection (Discharge) – High Voltage Outputs to Drive N-Channel Charge/Discharge FETs • Peripheral Features – Two configurable 8- or 16-bit Timers with Separate Prescaler, Optional Input Capture (IC), Compare Mode and CTC – SPI - Serial Programmable Interface – 12-bit Voltage ADC, Four External and One Internal ADC Inputs – High Resolution Coulomb Counter ADC for Current Measurements – Programmable Watchdog Timer • Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable via SPI ports – Power-on Reset – On-chip Voltage Regulator with Short-circuit Monitoring Interface – External and Internal Interrupt Sources – Sleep Modes: Idle, ADC Noise Reduction, Power-save, and Power-off • Additional Secure Authentication Features available only under NDA • Packages – 36-pad LGA – 28-lead TSOP • Operating Voltage: 1.8 - 9V • Maximum Withstand Voltage (High-voltage pins): 28V • Temperature Range: - 20°C to 85°C • Speed Grade: 1-4 MHz 8-bit Microcontroller with 8K/16K Bytes In-System Programmable Flash ATmega8HVA ATmega16HVA Preliminary 8024A–AVR–04/08 1 page ATmega8HVA/16HVA 2. Overview The ATmega8HVA/16HVA is a monitoring and protection circuit for 1-cell and 2-cell Li-ion appli- cations with focus on high security/authentication, accurate monitoring, low cost and high utilization of the cell energy. The device contains secure authentication features as well as autonomous battery protection during charging and discharging. The chip allows very accurate accumulated current measurements using an 18-bit ADC with a resolution of 0.84 µV. The fea- ture set makes the ATmega8HVA/16HVA a key component in any system focusing on high security, battery protection, accurate monitoring, high system utilization and low cost. Figure 2-1. Block Diagram PB3..0 PC0 VCC RESET/dW GND BATT VFET VREG PB0 Oscillator Circuits / Clock Generation Watchdog Oscillator Watchdog Timer Oscillator Sampling Interface Program Logic Power Supervision POR & RESET debugWIRE Flash Charger Detect PORTB (4) PORTC (1) SPI 8/16-bit T/C0 SRAM 8/16-bit T/C1 CPU DATA BUS EEPROM Security Module Voltage Regulator Voltage Regulator Monitor Interface PORTA (2) FET Control Battery Protection Voltage ADC VPTAT Voltage Reference Coulumb Counter ADC PA1..0 OC OD PV2 PV1 NV VREF VREFGND PI NI CF1N CF2N PA1..0 CF1P CF2P A combined step-up and linear voltage regulator ensures that the chip can operate with supply voltages as low as 1.8V for 1-cell applications. The regulator automatically switches to linear mode when the input voltage is sufficiently high, thereby ensuring a minimum power consump- tion at all times. For 2-cell applications, only linear regulation is enabled. The regulator capabilities, combined with an extremely low power consumption in the power saving modes, greatly enhances the cell energy utilization compared to existing solutions. The chip utilizes Atmel's patented Deep Under-voltage Recovery (DUVR) mode that supports pre-charging of deeply discharged battery cells without using a separate Pre-charge FET. 8024A–AVR–04/08 5 5 Page ATmega8HVA/16HVA 7.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 7-2. AVR CPU General Purpose Working Registers General Purpose Working Registers 70 R0 R1 R2 … R13 R14 R15 R16 R17 … R26 R27 R28 R29 R30 R31 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte 7.4.1 Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 7-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically imple- mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3 on page 12. 8024A–AVR–04/08 11 11 Page

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