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PDF AD2S1210-EP Data sheet ( Hoja de datos )
| Número de pieza | AD2S1210-EP | |
| Descripción | 10-Bit to 16-Bit R/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD2S1210-EP (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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Variable Resolution, 10-Bit to 16-Bit R/D
Converter with Reference Oscillator
AD2S1210-EP
FEATURES
Complete monolithic resolver-to-digital converter
3125 rps maximum tracking rate (10-bit resolution)
±2.5 arc minutes of accuracy
10-/12-/14-/16-bit resolution, set by user
Parallel and serial 10-bit to 16-bit data ports
Absolute position and velocity outputs
System fault detection
Programmable fault detection thresholds
Differential inputs
Incremental encoder emulation
Programmable sinusoidal oscillator on board
Compatible with DSP and SPI interface standards
5 V supply with 2.3 V to 5 V logic interface
Support defense and aerospace applications (AQEC)
Military temperature range ( −55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available upon request
APPLICATIONS
DC and ac servo motor control
Encoder emulation
Electric power steering
Electric vehicles
Integrated starter generators/alternators
Automotive motion sensing and control
GENERAL DESCRIPTION
The AD2S1210-EP is a complete 10-bit to 16-bit resolution
tracking resolver-to-digital converter, integrating an on-board
programmable sinusoidal oscillator that provides sine wave
excitation for resolvers.
The converter accepts 3.15 V p-p ± 27% input signals, in the range
of 2 kHz to 20 kHz on the sine and cosine inputs. A Type II
servo loop is employed to track the inputs and convert the input
sine and cosine information into a digital representation of the
input angle and velocity. The maximum tracking rate is 3125 rps.
Full details about this enhanced product, including theory of
operation, registers details, and applications information, are
available in the AD2S1210 data sheet, which should be
concluded in conjunction with this data sheet.
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
PINS
CRYSTAL
EXCITATION
OUTPUTS
REFERENCE
OSCILLATOR
(DAC)
VOLTAGE
REFERENCE
INTERNAL
CLOCK
GENERATOR
SYNTHETIC
REFERENCE
AD2S1210-EP
INPUTS
FROM
RESOLVER
ADC
ADC
TYPE II
TRACKING LOOP
FAULT
DETECTION
FAULT
DETECTION
OUTPUTS
ENCODER
EMULATION
OUTPUTS
POSITION VELOCITY CONFIGURATION
REGISTER REGISTER
REGISTER
DATA I/O
MULTIPLEXER
DATA BUS OUTPUT
RESET
DATA I/O
Figure 1.
PRODUCT HIGHLIGHTS
1. Ratiometric tracking conversion. The Type II tracking loop
provides continuous output position data without
conversion delay. It also provides noise immunity and
tolerance of harmonic distortion on the reference and
input signals.
2. System fault detection. A fault detection circuit can sense
loss of resolver signals, out-of-range input signals, input
signal mismatch, or loss of position tracking. The fault
detection threshold levels can be individually programmed
by the user for optimization within a particular application.
3. Input signal range. The sine and cosine inputs can accept
differential input voltages of 3.15 V p-p ± 27%.
4. Programmable excitation frequency. Excitation frequency
is easily programmable to a number of standard frequencies
between 2 kHz and 20 kHz.
5. Triple format position data. Absolute 10-bit to 16-bit angular
position data is accessed via either a 16-bit parallel port or a
4-wire serial interface. Incremental encoder emulation is in
standard A-quad-B format with direction output available.
6. Digital velocity output. 10-bit to 16-bit signed digital
velocity accessed via either a 16-bit parallel port or a 4-wire
serial interface.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
TIMING SPECIFICATIONS
AVDD = DVDD = 5.0 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter
fCLKIN
Description
Frequency of clock input
tCK Clock period (tCK = 1/fCLKIN)
t1 A0 and A1 setup time before RD/CS low
t2 Delay CS falling edge to WR/FSYNC rising edge
t3 Address/data setup time during a write cycle
t4 Address/data hold time during a write cycle
t5 Delay WR/FSYNC rising edge to CS rising edge
t6 Delay CS rising edge to CS falling edge
t7 Delay between writing address and writing data
t8 A0 and A1 hold time after WR/FSYNC rising edge
t9 Delay between successive write cycles
t10 Delay between rising edge of WR/FSYNC and falling edge of RD
t11 Delay CS falling edge to RD falling edge
t12 Enable delay RD low to data valid in configuration mode
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
t13 RD rising edge to CS rising edge
t14A Disable delay RD high to data high-Z
t14B Disable delay CS high to data high-Z
t15 Delay between rising edge of RD and falling edge of WR/FSYNC
t16 SAMPLE pulse width
t17 Delay from SAMPLE before RD/CS low
t18 Hold time RD before RD low
t19 Enable delay RD/CS low to data valid
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
t20 RD pulse width
t21 A0 and A1 set time to data valid when RD/CS low
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
t22 Delay WR/FSYNC falling edge to SCLK rising edge
t23 Delay WR/FSYNC falling edge to SDO release from high-Z
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
t24 Delay SCLK rising edge to DBx valid
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
t25 SCLK high time
t26 SCLK low time
t27 SDI setup time prior to SCLK falling edge
t28 SDI hold time after SCLK falling edge
Rev. 0 | Page 5 of 16
AD2S1210-EP
Limit at TMIN, TMAX
6.144
10.24
98
163
2
22
3
2
2
10
2 × tCK + 20
2
6 × tCK + 20
2
2
37
25
30
2
16
16
2
2 × tCK + 20
6 × tCK + 20
2
17
21
33
6
36
37
29
3
16
26
29
24
18
32
0.4 × tSCLK
0.4 × tSCLK
3
2
Unit
MHz min
MHz max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
5 Page 
12000
10000
8000
6000
4000
2000
0
126 127 128 129 130
CODES
Figure 9. Typical 10-Bit Angular Accuracy Histogram of Codes,
10,000 Samples, Hysteresis Enabled
20
18
16
14
12
10
8
6
4
2
0
0 4 8 12 16 20 24 28 32 36 40
TIME (ms)
Figure 10. Typical 16-Bit 10° Step Response
20
18
16
14
12
10
8
6
4
2
0
0 1 2 3 4 5 6 7 8 9 10
TIME (ms)
Figure 11. Typical 14-Bit 10° Step Response
AD2S1210-EP
20
18
16
14
12
10
8
6
4
2
0
0 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
TIME (ms)
Figure 12. Typical 12-Bit 10° Step Response
20
18
16
14
12
10
8
6
4
2
0
0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
TIME (ms)
Figure 13. Typical 10-Bit 10° Step Response
250
225
200
175
150
125
100
75
50
25
0
0
8 16 24 32 40 48 56 64 72
TIME (ms)
Figure 14. Typical 16-Bit 179° Step Response
80
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD2S1210-EP.PDF ] | |
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