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PDF CE2632 Data sheet ( Hoja de datos )
| Número de pieza | CE2632 | |
| Descripción | mixed signal CMOS monolithic stereo audio ADC | |
| Fabricantes | CEI Microelectronics | |
| Logotipo |  |
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DESCRIPTION
The CE2632 is a mixed signal CMOS monolithic stereo
audio ADC for consumer applications.
The ADC is 128-time oversampled. The sampled data are
digital filtered and decimated before sent out. A
switchabThe ADC utilizes 4-order Σ∆ architecture. The 1−
bit Σ∆ converter offers superior differential linearity, with
minimum distortion due to component mismatch, and high
tolerance to clock jitter. The internal digital filter has a 20K
bandwidth. The analog input is 1 vrms corresponding to
digital full scale value. The value greater than full scale
will be clipped.
FEATURES
• Stereo Audio ADC.
- 96dB SNR (A Weighted).
- -82 dB THD + N Ratio (A Weighted).
- 32K - 96 KHz. Sampling Rates.
- 91 dB channel separation.
• I2S, Left Justified Digital I/F Formats.
• 3.3 Volt Power Supply.
Applications
• Digital Surround Sound For Home Theatre
• AV Receiver
• Car Audio.
FMT NOHPF
CE2632
Control Interface
LIN 77
A/D
A/D
DECIMATION
FILTER
PCM
I/F
XCK
DOUT
BCK
LRCK
CEI Microelectronics Co. Ltd.
1-12
September 5, 2005
1 page  
CE2632
HIGH PASS FILTER
The processing path contain a switchable high pass filter. The function of this filter is to remove DC offset. The high pass filter
can be turn off by tied the NPHPF pin to ‘high’.
XCK REQUIREMENT
The CE2632 supports 384 and 256 times sampling clock for 32, 44.1, 48 Khz audio and 192 or 128 times for the 88.2 and 96
Khz audio. There is an clock frequency detection circuit to set up the system clock. .
Table (1): XCK Requirement
Sampling
Rate
32 K
44.1
48 K
96K
XCK Freq.
384*fs
256*fs
12.288 MHz 8.192 MHz
16.934 Mhz 11.2896 Mhz.
18.432 MHz 12.288 Mhz.
36.864 Mhz. 24.576 Mhz
DIGITAL AUDIO SERIAL INTERFACE
The audio serial interface is configured by the FMT pin. When FMT is low I2S format supported. Conversely left justified
format is supported. Figure 1 depicted the I2S and left justified formats.
Figure 1. Audio Serial Data Transfer Timing Diagram
LRCK
BCK
SDO
MSB
LEFT CHANNEL
LSB
0
1/fs
MSB
RIGHT CHANNEL
LSB
10
LRCK
BCK
SDO
FMT pin = ‘high’, Left justified format
LEFT CHANNEL
1/fs RIGHT CHANNEL
MSB
LSB MSB
10
FMT pin = ‘low’, I2S format
LSB
10
5-12 September 5, 2005
5 Page 
CE2632
Parameter
Characteristics
Min Typ Max Units
tkrsu
Audio LRCK Setup Time With Respect To Rising
10
Edge of BCK
tkrhd
Audio LRCK Hold Time With Respect To Rising
15
Edge of BCK
ns
ns
11-12
September 5, 2005
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CE2632.PDF ] | |
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