DataSheetWiki


IS43LD16160A fiches techniques PDF

ISSI - 256Mb Mobile LPDDR2 S4 SDRAM

Numéro de référence IS43LD16160A
Description 256Mb Mobile LPDDR2 S4 SDRAM
Fabricant ISSI 
Logo ISSI 





1 Page

No Preview Available !





IS43LD16160A fiche technique
IS43/46LD16160A
IS43/46LD32800A
256Mb (x16, x32) Mobile LPDDR2 S4 SDRAM
FEATURES
Low-voltage Core and I/O Power Supplies
VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V,
VDD1 = 1.70-1.95V
High Speed Un-terminated Logic(HSUL_12) I/O
Interface
Clock Frequency Range : 10MHz to 533MHz
(data rate range : 20Mbps to 1066Mbps per I/O)
Four-bit Pre-fetch DDR Architecture
Multiplexed, double data rate, command/ad-
dress inputs
Four internal banks for concurrent operation
Bidirectional/differential data strobe per byte of
data (DQS/DQS#)
Programmable Read/Write latencies(RL/WL)
and burst lengths(4,8 or 16)
ZQ Calibration
On-chip temperature sensor to control self re-
fresh rate
Partial –array self refresh(PASR)
Deep power-down mode(DPD)
Operation Temperature
Commercial (TC = 0°C to 85°C)
Industrial (TC = -40°C to 85°C)
Automotive, A1 (TC = -40°C to 85°C)
Automotive, A2 (TC = -40°C to 105°C)
OPTIONS
Configuration:
− 16Mx16 (4M x 16 x 4 banks)
− 8Mx32 (2M x 32 x 4 banks)
Package:
− 134-ball BGA for x16 / x32
− 168-ball PoP BGA for x32
DESCRIPTION
MAY 2016
The IS43/46LD16160A/32800A is 256Mbit CMOS
LPDDR2 DRAM. The device is organized as 4 banks
of 4Meg words of 16bits or 2Meg words of 32bits.
This product uses a double-data-rate architecture to
achieve high-speed operation. The double data rate
architecture is essentially a 4N prefetch architecture
with an interface designed to transfer two data words
per clock cycle at the I/O pins. This product offers fully
synchronous operations referenced to both rising and
falling edges of the clock. The data paths are internally
pipelined and 4n bits prefetched to achieve very high
bandwidth.
ADDRESS TABLE
Parameter
Row Addresses
Column Addresses
Bank Addresses
Refresh Count
8Mx32
R0-R12
C0-C7
BA0-BA1
4096
16Mx16
R0-R12
C0-C8
BA0-BA1
4096
KEY TIMING PARAMETERS(1)
Speed
Grade
-18
Data
Rate
(Mb/s)
1066
Write Read tRCD/
Latency Latency tRP(2)
4 8 Typical
-25 800
-3 667
3
2
6 Typical
5 Typical
Notes:
1. Other clock frequencies/data rates supported; please
refer to AC timing tables.
2. Please contact ISSI for Fast trcd/trp.
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. A
05/02/2016

PagesPages 30
Télécharger [ IS43LD16160A ]


Fiche technique recommandé

No Description détaillée Fabricant
IS43LD16160A 256Mb Mobile LPDDR2 S4 SDRAM ISSI
ISSI

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche