PDF IS43LR32800F Data sheet ( Hoja de datos )

Número de pieza	IS43LR32800F
Descripción	2M x 32Bits x 4Banks Mobile DDR SDRAM
Fabricantes	ISSI
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No Preview Available ! IS43/46LR32800F 2M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR32800F is 268,435,456 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 2,097,152 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 32-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS. Features • JEDEC standard 1.8V power supply. • VDD = 1.8V, VDDQ = 1.8V • Four internal banks for concurrent operation • MRS cycle with address key programs - CAS latency 2, 3 (clock) - Burst length (2, 4, 8, 16) - Burst type (sequential & interleave) • Fully differential clock inputs (CK, /CK) • All inputs except data & DM are sampled at the rising edge of the system clock • Data I/O transaction on both edges of data strobe • Bidirectional data strobe per byte of data (DQS) • DM for write masking only • Edge aligned data & data strobe output • Center aligned data & data strobe input • 64ms refresh period (4K cycle) • Auto & self refresh • Concurrent Auto Precharge • Maximum clock frequency up to 200MHZ • Maximum data rate up to 400Mbps/pin • Power Saving support - PASR (Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - Deep Power Down Mode - Programmable Driver Strength Control by Full Strength, or 3/4, 1/2, 1/4, 1/8 of Full Strength • Status Register Read (SRR) • LVCMOS compatible inputs/outputs • Packages: - 90-Ball FBGA - 152-Ball PoP BGA Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Rev. A \| February 2013 www.issi.com - [email protected] 1 1 page Figure3 : Functional Block Diagram IS43/46LR32800F /CK CK CKE /CS /RAS /CAS /WE DM0 ~ DM3 PASR Extended Mode Register Self refresh Logic & timer Internal Row Counter Row Active Row Pre Decoder Refresh Column Active Column Pre Decoder Write Data Register 2-bit Prefetch Unit X64 X32 2Mx32 BANK 3 2Mx32 BANK 2 2Mx32 BANK 1 2Mx32 BANK 0 Memory Cell Array Column Decoders \| \| 64 \| \| DS DQ0 \|. \| . . 32 \| . . . \|. DQ31 Bank Select Column Add Counter A0 A1 Address Register Burst Counter A11 CAS BA0 Mode Register Latency Data Out Control BA1 DQS0 ~ DQS3 Data Strobe Transmitter DS Data Strobe Receiver Rev. A \| February 2013 www.issi.com - [email protected] 5 5 Page IS43/46LR32800F Figure 7: Power up Sequence VDD VDDQ CLK /CLK CKE Command1 A0~A9, A11 A10 BA0, BA1 DQS, DQ DM T0 T1 LVCMOS HIGH LEVEL NOP2 tCL tIS tIH NOP PCG Ta0 AREF All Banks tIS tIH High-Z Tb0 Tc0 Td0 AREF MRS tIS tIH CODE tIS tIH CODE tIS tIH BA0=L, BA1=L MRS CODE CODE BA0=L, BA1=H Te0 ACT RA RA BA Tf0 NOP3 T = 200 µs tCK Power-up: VDD and CLK stable tRP4 tRFC4 Don’ t care tRFC4 tMRD4 tMRD4 Load Standard Mode Load Extended Mode Register Register Notes: 1. 2. 3. 4. PCG = PRECHARGE command, MRS = LOAD MODE REGISTER command, AREF = AUTOREFRESH command, ACT = ACTIVE command, RA = Row address, BA = Bank address. NOP or DESELECT commands are required for at least 200μs. Other valid commands are possible. NOPs or DESELECTs are required during this time. Rev. A \| February 2013 www.issi.com - [email protected] 11 11 Page

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