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PDF PI6ULS5V9515A Data sheet ( Hoja de datos )
| Número de pieza | PI6ULS5V9515A | |
| Descripción | I2C Bus/SMBus Repeater | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6ULS5V9515A
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I2C Bus/SMBus Repeater
Features
2 channel, bidirectional buffer
drivers on and off. This can be used to isolate a badly
behaved slave on power-up until after the system power-
up reset. It should never change state during an I2C-bus
I2C-bus and SMBus compatible
operation because disabling during a bus operation will
Operating supply voltage range of 2.3 V to 3.6 V
Active HIGH repeater enable input
hang the bus and enabling part way through a bus cycle
could confuse the I2C-bus parts being enabled. The
enable pin should only change state when the global bus
Open-drain input/outputs
Lock-up free operation
Supports arbitration and clock stretching across the
and the repeater port are in an idle state to prevent
system failures.
The output low levels for sides are approximately 0.5
V, but the input voltage of each internal buffer must be
repeater
Accommodates Standard-mode and Fast-mode I2C-
70 mV lower (0.43V) or even more lower. When the
output internally is driven low the low is not recognized
as a low by the input.. This prevents a lockup condition
bus devices and multiple masters
Powered-off high-impedance I2C-bus pins
5.5 V tolerant I2C-bus and enable pins
from occurring when the input low condition is released.
Two or more PI6ULS5V9515A devices can’t be
used in series. The PI6ULS5V9515A design does not
allow this configuration. Since there is no direction pin,
0 Hz to 400 kHz clock frequency (the maximum
slightly different valid low-voltage levels are used to
system operating frequency may be less than 400
kHz because of the delays added by the repeater)
avoid lockup conditions between the input and the
output of each repeater. A valid low applied at the input
of a PI6ULS5V9515A will be propagated as a buffered
ESD protection exceeds 4KV HBM per JESD22-
A114
Package: MSOP-8, SOIC-8 and DFN2x3-8L
low with a slightly higher value on the output. When this
buffered low is applied to another PI6ULS5V9515A-
type device in series, the second device does not
recognize it as a valid low and will not propagate it as a
buffered low again.
Description
The device contains a power-up control circuit that
sets an internal latch to prevent the output circuits
The PI6ULS5V9515A is a CMOS integrated circuit
intended for I2C bus and SMBus systems applications.
The device contains two identical bidirectional open-
drain buffer circuits that enable I2C and similar bus
from becoming active until Vcc is at a valid level (Vcc =
2.3 V).
As with the standard I2C system, pull-up resistors are
required to provide the logic-high levels on the buffered
systems to be extended without degradation of system
performance.
bus. The PI6ULS5V9515A has standard open-collector
configuration of the I2C bus. The size of these pull-up
The PI6ULS5V9515A enables the system designer resistors depends on the system, but each side of the
to isolate two halves of a bus for both voltage and
capacitance, accommodating more I2C devices or longer
trace length. It also permits extension of the I2C-bus by
repeater must have a pull-up resistor. The device is
designed to work with Standard mode and Fast mode I2C
devices in addition to SMBus devices. Standard mode
providing bidirectional buffering for both the data (SDA) I2C devices only specify 3mA in a generic I2C system,
and the clock (SCL) lines, thus allowing two buses of
400 pF to be connected in an I2C application.
where Standard mode devices and multiple masters are
possible. Under certain conditions, higher termination
The PI6ULS5V9515A has an EN pin to turn the currents can be used.
2015-10-0002
PT0455-3
10/20/15
1
1 page  
PI6ULS5V9515A
I2C-Bus/SMBus Repeater
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Functional Description
The PI6ULS5V9515A is a CMOS integrated circuit intended for I2C bus and SMBus systems applications. The device
contains two identical bidirectional open-drain buffer circuits that enable I2C and similar bus systems to be extended without
degradation of system performance.
The PI6ULS5V9515A enables the system designer to isolate two halves of a bus for both voltage and capacitance.,
accommodating more I2C devices or longer trace length. It also permits extension of the I2C-bus by providing bidirectional
buffering for both the data (SDA) and the clock (SCL) lines, thus allowing two buses of 400 pF to be connected in an I2C
application.
The PI6ULS5V9515A has an EN pin to turn the drivers on and off. This can be used to isolate a badly behaved slave on
power-up until after the system power-up reset. It should never change state during an I2C-bus operation because disabling during
a bus operation will hang the bus and enabling part way through a bus cycle could confuse the I2C-bus parts being enabled. The
enable pin should only change state when the global bus and the repeater port are in an idle state to prevent system failures.
The output low levels for sides are approximately 0.5 V, but the input voltage of each internal buffer must be 70 mV lower
(0.43V) or even more lower. When the output internally is driven low he low is not recognized as a low by the input.. This
prevents a lockup condition from occurring when the input low condition is released.
Two or more PI6ULS5V9515A devices can’t be used in series. The PI6ULS5V9515A design does not allow this configuration.
Since there is no direction pin, slightly different valid low-voltage levels are used to avoid lockup conditions between the input
and the output of each repeater. A valid low applied at the input of a PI6ULS5V9515A will be propagated as a buffered low with a
slightly higher value on the output. When this buffered low is applied to another PI6ULS5V9515A-type device in series, the
second device does not recognize it as a valid low and will not propagate it as a buffered low again.
The device contains a power-up control circuit that sets an internal latch to prevent the output circuits from becoming
active until Vcc is at a valid level (Vcc = 2.3 V).
As with the standard I2C system, pull-up resistors are required to provide the logic-high levels on the buffered bus. The
PI6ULS5V9515A has standard open-collector configuration of the I2C bus. The size of these pull-up resistors depends on the
system, but each side of the repeater must have a pull-up resistor. The device is designed to work with Standard mode and Fast
mode I2C devices in addition to SMBus devices. Standard mode I2C devices only specify 3 mA in a generic I2C system, where
Standard mode devices and multiple masters are possible. Under certain conditions, higher termination currents can be used.
Application Information
A typical application is shown in Figure 4. In this example, the system master is running on a 3.3 V I2C-bus while the slave is
connected to a 5V bus. Both buses run at 400 kHz. Master devices can be placed on either bus.
The PI6ULS5V9515A is 5V tolerant, so it does not require any additional circuitry to translate between different bus voltages.
When one side of the PI6ULS5V9515A is pulled LOW by a device on the I2C-bus, a CMOS hysteresis type input detects the
falling edge and causes the internal driver on the other side to turn on, thus causing the other side to also go LOW. The side driven
LOW by the PI6ULS5V9515A will typically be at VOL = 0.5 V.
Figure 5 and Figure 6 show the waveforms that are seen in a typical application. If the bus master in Figure4 writes to the slave
through the PI6ULS5V9515A, Bus 0 has the waveform shown in Figure 5. This looks like a normal I2C transmission until the
falling edge of the eighth clock pulse. At that point, the master releases the data line (SDA) while the slave pulls it low through the
PI6ULS5V9515A. Because the VOL of the PI6ULS5V9515A typically is around 0.5V, a step in the SDA is seen. After the master
has transmitted the ninth clock pulse, the slave releases the data line.
On the Bus 1 side of the PI6ULS5V9515A, the clock and data lines have a positive offset from ground equal to the VOL of the
PI6ULS5V9515A. After the eighth clock pulse, the data line is pulled to the VOL of the slave device, which is very close to ground
in the example.
It is important to note that any arbitration or clock-stretching events on Bus 1 require that the VOL of the devices on Bus 1 be
70 mV below the VOL of the PI6ULS5V9515A (see VOL - VILC in Electrical Characteristics) to be recognized by the
PI6ULS5V9515A and transmitted to Bus 0.
2015-10-0002
PT0455-3
10/20/15
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet PI6ULS5V9515A.PDF ] | |
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