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PDF PI90LV9637 Data sheet ( Hoja de datos )

Número de pieza PI90LV9637
Descripción LVDS High-Speed Differential Line Receivers
Fabricantes Pericom Semiconductor 
Logotipo Pericom Semiconductor Logotipo



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No Preview Available ! PI90LV9637 Hoja de datos, Descripción, Manual

PI90LV9637
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LVDS High-Speed Differential
Line Receivers
Features
Signaling Rates >400Mbps (200 MHz)
Single 3.3V Power Supply Design
Accepts ±350mV (typical) Differential Swing
Maximum Differential Skew of 0.35ns
Maximum Propagation Delay of 4.7ns
Low Voltage TTL (LVTTL) Outputs
Industrial Temperature Operating Range: -40°C to 85°C
Open, Short, and Terminated Fail Safe
Meets or Exceeds ANSI/TIA/EIA-644 LVDS Standard
• Packaging (Pb-free & Green available):
-8-Pin SOIC (W)
-8-Pin MSOP (U)
Description
The PI90LV9637 is a differential line receiver that use low-voltage
differential signaling (LVDS) to support data rates in excess of 400
Mbps. These products are designed for applications requiring
high-speed, low-power consumption and low noise generation.
A differential input signal (350mV) is translated by the device to 3V
CMOS output level.
Applications
Applications include point-to-point and multidrop baseband data
transmission over controlled impedance media of approximately
100-ohms. The transmission media can be printed circuit board
traces, backplanes, or cables.
The PI90LV9637provides new alternatives to RS-232, PECL, and
ECL devices for high-speed, point-to-point interface applications.
PI90LV9637
8-Pin
W,U
08-0295
1
PS8667C
11/11/08

1 page




PI90LV9637 pdf
PI90LV9637
11223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455L6677V8899D001122S3344H5566i77g8899h0011-22S11p2233e44e5566d7788D9900i11f22f33e4455r66e7788n99t00i11a2233l44L5566i77n8899e0011R2211e2233c44e55i66v7788e99r0011s22
Parameter Measurement Information
Generator
50Ω
RIN+
RIN–
50Ω
R ROUT
CL
Receiver Enabled
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
RIN-
RIN+
ROUT
0V (Differential)
tPLHD
80%
1.5V
20%
tTLH
VID = 200m+V1.2V
tPHLD
80%
1.5V
+1.3V
+1.1V
20%
tTHL
VOL
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
CL includes load and test jig capacitance.
S1 = VCC for TPZL, and TPLZ measurements
S1= GND for tPZH and tPHZ measurements
Generator
EN RIN+
RIN–
50Ω
VCC
Device
Under
Test
S1
RL
ROUT
CL
08-0295
Figure 3. Receiver Three-State Delay Test Circuit
5
PS8667C
11/11/08

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