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PDF NCV1455B Data sheet ( Hoja de datos )
| Número de pieza | NCV1455B | |
| Descripción | Timers | |
| Fabricantes | ON Semiconductor | |
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MC1455, MC1455B,
NCV1455B
Timers
The MC1455 monolithic timing circuit is a highly stable controller
capable of producing accurate time delays or oscillation. Additional
terminals are provided for triggering or resetting if desired. In the time
delay mode, time is precisely controlled by one external resistor and
capacitor. For astable operation as an oscillator, the free−running
frequency and the duty cycle are both accurately controlled with two
external resistors and one capacitor. The circuit may be triggered and
reset on falling waveforms, and the output structure can source or sink
up to 200 mA or drive MTTL circuits.
• Direct Replacement for NE555 Timers
• Timing from Microseconds through Hours
• Operates in Both Astable and Monostable Modes
• Adjustable Duty Cycle
• High Current Output Can Source or Sink 200 mA
• Output Can Drive MTTL
• Temperature Stability of 0.005% per °C
• Normally ON or Normally OFF Output
10 k
0.1 mF
5
0.01 mF
1.0 k
38
46
2 MC1455 7
R
1 1.0 mF
MT2
20 M G
C
−10 V
Load
MT1
1N4003
t = 1.1; R and C = 22 sec
Time delay (t) is variable by
changing R and C (see Figure 16).
1N4740
3.5 k
−
10
mF
250 V +
http://onsemi.com
MARKING
DIAGRAMS
8
1
P1 SUFFIX
PLASTIC PACKAGE
CASE 626
XXXXXXXXX
AWL
YYWW
8
1
D SUFFIX
PLASTIC PACKAGE
CASE 751
8
XXXXXX
ALYW
1
xx = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page ___ of this data sheet.
(Create − Named − OrderingInfoText.)
Figure 1. 22 Second Solid State Time Delay Relay Circuit
VR ICC VCC
VCC
8
5k
6
Threshold
5
Control Voltage
5k
Trigger
2
5k
+
Comp
−A
+
Comp
−B
1
Gnd
Flip
R Flop
Q
S Inhibit/
Reset
4
Reset
7
Discharge
3
Output
+
0.01 mF
VO
Reset
5
Control
Voltage
3
Output
ISink
ISource
48
VCC
MC1455
700
7
Discharge
Threshold
6 Ith
Gnd Trigger
12
2.0 k
VS
Test circuit for measuring DC parameters (to set output and
measure parameters):
a) When VS w 2/3 VCC, VO is low.
b) When VS v 1/3 VCC, VO is high.
c) When VO is low, Pin 7 sinks current. To test for Reset, set VO
c) high, apply Reset voltage, and test for current flowing into Pin 7.
c) When Reset is not in use, it should be tied to VCC.
Figure 2. Representative Block Diagram
Figure 3. General Test Circuit
© Semiconductor Components Industries, LLC, 2004
March, 2004 − Rev. 8
1
Publication Order Number:
MC1455/D
1 page  
MC1455, MC1455B, NCV1455B
Control Voltage
Threshold
Comparator
Trigger
Comparator
Flip−Flop
Output
VCC
4.7 k 830 4.7 k 1.0 k
6.8 k
5.0 k
Threshold
7.0 k
Trigger
Reset
Discharge
Gnd
10 k
cb
5.0 k e 4.7 k
Reset
Discharge
100 k
100
5.0 k
Figure 13. Representative Circuit Schematic
3.9 k
cb
Output
220
4.7 k
GENERAL OPERATION
The MC1455 is a monolithic timing circuit which uses an
external resistor − capacitor network as its timing element. It
can be used in both the monostable (one−shot) and astable
modes with frequency and duty cycle controlled by the
capacitor and resistor values. While the timing is dependent
upon the external passive components, the monolithic circuit
provides the starting circuit, voltage comparison and other
functions needed for a complete timing circuit. Internal to the
integrated circuit are two comparators, one for the input
signal and the other for capacitor voltage; also a flip−flop and
digital output are included. The comparator reference
voltages are always a fixed ratio of the supply voltage thus
providing output timing independent of supply voltage.
has been triggered by an input signal, it cannot be retriggered
until the present timing period has been completed. The time
that the output is high is given by the equation t = 1.1 RA C.
Various combinations of R and C and their associated times
are shown in Figure 16. The trigger pulse width must be less
than the timing period.
A reset pin is provided to discharge the capacitor, thus
interrupting the timing cycle. As long as the reset pin is low,
the capacitor discharge transistor is turned “on” and
prevents the capacitor from charging. While the reset
voltage is applied the digital output will remain the same.
The reset pin should be tied to the supply voltage when not
in use.
Monostable Mode
In the monostable mode, a capacitor and a single resistor
are used for the timing network. Both the threshold terminal
and the discharge transistor terminal are connected together
in this mode (refer to circuit in Figure 14). When the input
voltage to the trigger comparator falls below 1/3 VCC, the
comparator output triggers the flip−flop so that its output
sets low. This turns the capacitor discharge transistor “off”
and drives the digital output to the high state. This condition
allows the capacitor to charge at an exponential rate which
is set by the RC time constant. When the capacitor voltage
reaches 2/3 VCC, the threshold comparator resets the
flip−flop. This action discharges the timing capacitor and
returns the digital output to the low state. Once the flip−flop
+VCC (5.0 V to 15 V)
Reset
RL 4
Output
VCC
8
Discharge
7
RA
3
RL 2
Trigger
MC1455
1
6
Threshold
5
Control
Voltage
C
0.01 mF
Figure 14. Monostable Circuit
http://onsemi.com
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