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PI2EQXDP101-A fiches techniques PDF

Pericom Semiconductor - 1 to 1 DisplayPort ReDriver

Numéro de référence PI2EQXDP101-A
Description 1 to 1 DisplayPort ReDriver
Fabricant Pericom Semiconductor 
Logo Pericom Semiconductor 





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PI2EQXDP101-A fiche technique
PI2EQXDP101-A
1 to 1 DisplayPort™ ReDriver™
Features
• DisplayPort™ 1.1a operation at reduced bit rate (1.62Gbps)
and high bit rate (2.7Gbps)
• Jitter elimination circuits automatically adjust link via training
path
àà Pre-Emphasis, and output swing
• Can support all 4 levels of output swing and 4 levels output
pre-emphasis, as specified in the DisplayPort 1.1a spec.
• AUX interception circuit only listens to the link training, but
does not affect link training
• Low insertion loss across the AUX signal path (0.35dB
@1Mbps)
• Output can support dual mode DP by providing DDC signals
across the AUX_sink pins
àà Using Cable Detect pin from DP connector (pin 13),
the switch can toggle between DP and TMDS mode.
• Automatic power down state when HPD signal is LOW
• Enters low power mode when no data signal is present
• Dual power supply (1.5V and 3.3V)
• 2KV HBM ESD protection
• 50 ohm output termination can be turned off when port is off
àà Port is turned off automatically when not needed
• Package (Pb-Free & Green available)
àà 36-pin TQFN (ZF)
Description
The PI2EQXDP101-Ais a one Input and one Output DisplayPort™
ReDriver™ that support a maximum data rate of 2.7 Gbps through
each channel, which results in a total of 10.8Gbps through-put.
Output Level Swing and Output Pre-emphasis and number of
active lanes are controlled by decoding the AUX command
during link initialization. Also, utilizing the HPD signals from
each DisplayPort port, the PI2EQXDP101-A can automatically
enter power down state. Or, if the graphics driver is off and has
no output signal, Pericom’s PI2EQXDP101-A can automatically
enter low power mode, even if an active monitor is attached.
Block Diagram
Pin Diagram (Top-side View)
IN [3:0]±
Equalizer
Pre-emphasis
HPD_Sink
CAD_Sink
Logics
HPD SRC
CAD SRC
Bias
OUT [3:0]±
AUX_SRC+
AUX_SRC-
SCL
SDA
AUX CH
interpreter
register
AUX
Pass
through
DDC_SCL/AUX+
DDC_SDA/AUX-
DDC
Pass
through
IN0+ 1
IN0- 2
36 35 34 33 32 31 30 29
28
27
OUT0+
OUT0-
IN1+ 3
26 OUT1+
IN1- 4
VDD15 5
25 OUT1-
24 GND
IN2+ 6
23 OUT2+
IN2- 7
22 OUT2-
GND 8
21 VDD15
IN3+ 9
20 OUT3+
IN3- 10
19 OUT3-
11 12 13 14 15 16 17 18
10-0194
1
P-0.3
07/09/10

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