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IS43DR81280C fiches techniques PDF

ISSI - DDR2 DRAM

Numéro de référence IS43DR81280C
Description DDR2 DRAM
Fabricant ISSI 
Logo ISSI 





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IS43DR81280C fiche technique
IS43/46DR81280C
IS43/46DR16640C
128Mx8, 64Mx16 DDR2 DRAM
FEATURES
Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Double data rate interface: two data transfers
per clock cycle
Differential data strobe (DQS, DQS)
4-bit prefetch architecture
On chip DLL to align DQ and DQS transitions
with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL) 3, 4, 5, 6 and 7
supported
Posted CAS and programmable additive latency
(AL) 0, 1, 2, 3, 4, 5 and 6 supported
WRITE latency = READ latency - 1 tCK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength, full and
reduced strength options
On-die termination (ODT)
ADVANCED INFORMATION
DESCRIPTION
MAY 2013
ISSI's 1Gb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double-data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer two
data words per clock cycle at the I/O balls.
ADDRESS TABLE
Parameter
Configuration
Refresh Count
128M x 8
16M x 8 x 8
banks
8K/64ms
64M x 16
8M x 16 x 8
banks
8K/64ms
Row Addressing 16K (A0-A13) 8K (A0-A12)
Column
Addressing
1K (A0-A9)
Bank Addressing BA0 - BA2
1K (A0-A9)
BA0 - BA2
Precharge
Addressing
A10
A10
OPTIONS
Configuration(s):
128Mx8 (16Mx8x8 banks): IS43/46DR81280C
64Mx16 (8Mx16x8 banks): IS43/46DR16640C
Package:
x8: 60-ball BGA (8mm x 10.5mm)
x16: 84-ball WBGA (8mm x 12.5mm)
Timing – Cycle time
2.5ns @CL=5 DDR2-800D
2.5ns @CL=6 DDR2-800E
3.0ns @CL=5 DDR2-667D
3.75ns @CL=4 DDR2-533C
5ns @CL=3 DDR2-400B
Temperature Range:
Commercial (0°C Tc 85°C)
Industrial (-40°C Tc 95°C; -40°C Ta 85°C)
Automotive, A1 (-40°C Tc 95°C; -40°C Ta 85°C)
Automotive, A2 (-40°C Tc; Ta 105°C)
Tc = Case Temp, Ta = Ambient Temp
KEY TIMING PARAMETERS
Speed Grade -25D -3D
tRCD
12.5 15
tRP 12.5 15
tRC 55 55
tRAS
40 40
tCK @CL=3
55
tCK @CL=4
3.75 3.75
tCK @CL=5
2.5 3
tCK @CL=6
2.5 —
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. 00A
6/4/2013

PagesPages 30
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