PDF TLK4250 Data sheet ( Hoja de datos )

Número de pieza	TLK4250
Descripción	QUAD 1.0 to 2.5 Gbpss TRANSCEIVER
Fabricantes	Texas
Logotipo
Hay una vista previa y un enlace de descarga de TLK4250 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas
No Preview Available ! D Hot Plug Protection D Quad 1.0 to 2.5 Gigabits Per Second (Gbps) Serializer/Deserializer D Independent Channel Operation D 2.5-V Power Supply for Low Power Operation D Selectable Signal Preemphasis for Serial Output D Interfaces to Backplane, Copper Cables, or Optical Converters D Lock Indication and Sync Mode for Fast Initialization D 18-Bit Parallel Buses for Flexible Interface Applications TLK4250 QUAD 1.0 to 2.5 Gbps TRANSCEIVER SWRS025C − APRIL 2004 − REVISED JULY 2007 D On-Chip PLL Provides Clock Synthesis From Low-Speed Reference D Receiver Differential Input Thresholds 200 mV Min D Rated for Industrial Temperature Range D Typical Power: 1700 mW at 2.5 Gbps D Ideal for High-Speed Backplane Interconnect and Point-to-Point Data Link D Internal Passive Receive Equalization D Small Footprint 19 mm x 19 mm, 289-Ball PBGA Package description The TLK4250 device is a four-channel, multi-gigabit transceiver used in high-speed bidirectional point-to-point data transmission systems. The four channels in the transceiver are configured as four separate links. The transceiver supports an effective serial interface speed of 1.0 Gbps to 2.5 Gbps per channel, providing up to 2.25 Gbps of data bandwidth per channel. The primary application of the transceiver is to provide high-speed I/O data channels for point-to-point baseband data transmission over controlled impedance media of approximately 50 Ω. The transmission media can be a printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer depend on the attenuation characteristics of the media and the noise coupling to the environment. The transceiver can also replace parallel data transmission architectures by providing a reduction in the number of traces, connector pins, and transmit/receive pins. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an optical link. The data is then reconstructed into its original parallel format. It offers significant power and cost savings over current solutions, as well as scalability for higher data rate in the future. The transceiver performs the data parallel-to-serial and serial-to-parallel conversions. The clock extraction functions as a physical layer interface device. The serial transceiver interface operates at a maximum data rate of 2.5 Gbps. Each transmitter latches 18-bit parallel data at a rate based on the supplied reference clock (GTx_CLK). The 18-bit parallel data is internally encoded into 20 bits by framing the 18-bit data with start and stop bits. The resulting 20-bit frame is then transmitted differentially at 20 times the reference clock (GTx_CLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the recovered clock (Rx_CLK). It then extracts the 18 bits of data from the 20-bit wide data resulting in 18 bits of parallel data at the receive data terminals (RDx[0:17]). This results in an effective data payload of 0.9 Gbps to 2.25 Gbps (18 bits data x GTx_CLK frequency) per channel. The transceiver provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer, allowing the protocol device a functional self-check of the physical interface. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2004 − 2007, Texas Instruments Incorporated WWW.TI.COM 1 1 page NAME DINRAP DINRAN TERMINAL NO. A6 A7 DINRBP DINRBN F17 G17 DINRCP DINRCN P17 R17 DINRDP DINRDN U4 U3 DOUTTAP DOUTTAN A3 A4 DOUTTBP DOUTTBN C17 D17 DOUTTCP DOUTTCN L17 M17 DOUTTDP DOUTTDN U7 U6 ENABLEA ENABLEB ENABLEC ENABLED GTA_CLK GTB_CLK GTC_CLK GTD_CLK SYNCA SYNCB SYNCC SYNCD LOOPENA H5 E10 M9 J6 E2 B13 K13 P8 F4 D12 N10 K5 H4 LOOPENB D10 LOOPENC P12 LOOPEND M4 LOCKBA LOCKBB LOCKBC LOCKBD PREEMPHA PREEMPHB PREEMPHC PREEMPHD G5 E11 N9 L4 A5 E17 N17 U5 TLK4250 QUAD 1.0 to 2.5 Gbps TRANSCEIVER SWRS025C − APRIL 2004 − REVISED JULY 2007 Terminal Functions TYPE DESCRIPTION Input Serial receive inputs. DINRxP and DINRxN together are the differential serial inputs that interface from a copper or an optical I/F module. Output (high-z power up) Serial transmit outputs. DOUTTxP and DOUTTxN are differential serial outputs that interface to copper or an optical I/F module. These terminals transmit NRZ data at a rate of 20 times the GTx_CLK value. DOUTTxP and DOUTTxN are put in a high-impedance state when LOOPENx is high and are active when LOOPENx is low. During power-on reset these terminals are high impedance. Input (w/pullup) Device enable. When this terminal is held low, the device is placed in power-down mode. When asserted high while the device is in power-down mode, the transceiver goes into power-on reset before beginning normal operation. Input Reference clock. GTx_CLK is a continuous external input clock that synchronizes the transmitter interface TDx. The frequency range of GTx_CLK is 50 MHz to 125 MHz. The transmitter uses the rising edge of this clock to register the 18-bit input data (TDx) for serialization. Input (w/pulldown) Fast synchronization. When asserted high, the transmitter substitutes the 18-bit pattern 111111111000000000 so that when the start/stop bits are framed around the data, the receiver can immediately detect the proper deserialization boundary. This is typically used during initialization of the serial link. Input (w/pulldown) Loop enable. When LOOPENx is active high, the internal loop-back path is activated. The transmitted serial data is directly routed internally to the inputs of the receiver. This provides a self-test capability with the protocol device. The DOUTTxP and DOUTTxN outputs are held in a high-impedance state during the loop-back test. LOOPENx is held low during standard operational state with external serial outputs and inputs active. Output Receiver lock. When this signal is asserted low, it indicates that the receiver has acquired bit synchronization on the data stream and has located the start/stop bits so that the deserialized data presented on the parallel receive bus is properly received. Input Preemphasis. When asserted, the serial transmit outputs have extra output swings on the first bit of any run length of save value bits. If the run length of output bits is one, then that bit has larger output swings. WWW.TI.COM 5 5 Page TLK4250 QUAD 1.0 to 2.5 Gbps TRANSCEIVER SWRS025C − APRIL 2004 − REVISED JULY 2007 reference clock input The reference clock (GTx_CLK) is an external input clock that synchronizes the transmitter interface. The reference clock is then multiplied in frequency 10 times to produce the internal serialization bit clock. The internal serialization bit clock is frequency locked to the reference clock and clocks out the serial transmit data on both its rising and falling edges, providing a serial data rate that is 20 times the reference clock. The receiver tracking logic uses clock phases from the internal PLL as it aligns the recovered clock phase with the incoming serial data stream; therefore, the input reference clock (GTX_CLK) is needed even if the transmit function of the TLK4250 is not being used. The receiver function has the ability to track an incoming serial data stream that is within ±200 ppm of the data rate that is set by GTX_CLK. This allows the use of clock sources with ±100 ppm frequency tolerance. operating frequency range The transceiver may operate at a serial data rate between 1.0 Gbps to 2.5 Gbps. GTx_CLK must be within ±100 PPM of the desired parallel data rate clock. Each individual channel may operate at a different rate. testability The transceiver has a comprehensive suite of built-in self-tests. The loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. The ENABLEx terminal allows for all circuitry to be disabled so that a quiescent current test can be performed. loop-back testing The transceiver can provide a self-test function by enabling (LOOPENx) the internal loop-back path. Enabling this terminal causes serial transmitted data to be routed internally to the receiver. The parallel data output can be compared to the parallel input data for functional verification. (The external differential output is held in a high-impedance state during the loop-back testing.) power-on reset On application of minimum valid power, the transceiver generates a power-on reset. During the power-on reset, the RDx terminals are 3-stated and Rx_CLK is held low. The length of the power-on reset cycle depends on the GTx_CLK frequency, but is less than 1 ms in duration. WWW.TI.COM 11 11 Page

Páginas	Total 21 Páginas
PDF Descargar	[ Datasheet TLK4250.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
TLK4250	QUAD 1.0 to 2.5 Gbpss TRANSCEIVER	Texas

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar