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PDF CDP1821C3 Data sheet ( Hoja de datos )
| Número de pieza | CDP1821C3 | |
| Descripción | High-Reliability CMOS 1024-Word x 1-Bit Static RAM | |
| Fabricantes | Intersil Corporation | |
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CDP1821C/3
March 1997
High-Reliability CMOS
1024-Word x 1-Bit Static RAM
Features
Description
• Static CMOS Silicon-On-Sapphire Circuitry CD4000-
Series Compatible
• Compatible with CDP1800-Series Microprocessors at
Maximum Speed
• Fast Access Time. . . . . . . . . . . 100ns Typ. at VDD = 5V
• Single Voltage Supply
• No Precharge or External Clocks Required
• Low Quiescent and Operating Power
• Separate Data Inputs and Outputs
• High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of VDD
• Memory Retention for Standby Battery Voltage Down
to 2V at +25oC
• Latch-Up-Free Transient-Radiation Tolerance
The CDP1821C/3 is a 1024-word x 1-bit CMOS silicon-on-sap-
phire (SOS), fully static, random-access memory designed for
use in CDP1800 microprocessor systems. This device has a
recommended operating voltage range of 4V to 6.5V.
The output state of the CDP1821C/3 is a function of the
input address and chip-select states only. Valid data will
appear at the output in one access time following the latest
address change to a selected chip. After valid data appears,
the address may be changed immediately. It is not neces-
sary to clock the chip-select input or any other input terminal
for fully static operation; therefore the chip-select input may
be used as an additional address input. When the device is
in an unselected state (CS = 1), the internal write circuitry
and output sense amplifier are disabled. This feature allows
the three-state data outputs from many arrays to be OR-tied
to a common bus for easy memory expansion.
Ordering Information
PACKAGE
SBDIP
TEMP. RANGE
-55oC to +125oC
PART
NUMBER PKG. NO.
CDP1821CD3 D16.3
Pinout
CDP1821C/3
(SBDIP)
TOP VIEW
CS 1
A0 2
A1 3
A2 4
A3 5
A4 6
DO 7
VSS 8
16 VDD
15 DI
14 RD/WR
13 A9
12 A8
11 A7
10 A6
9 A5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-5
File Number 2983.1
1 page  
CDP1821C/3
Write Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF
PARAMETER
SYMBOL
VDD
(V)
-55oC, +25oC
MIN MAX
+125oC
MIN MAX
Write Cycle Time
tWC 5 300 - 420 -
Address Setup Time (Note 1)
tAS 5 60 - 84 -
Address Hold Time (Note1)
tAH 5 130 - 180 -
Input Data Setup Time (Note 1)
tDS 5 90 - 125 -
Input Data Hold Time (Note 1)
tDH 5 60 - 84 -
Read/Write Pulse Width Low (Note 1)
tWL
5
110
-
155
-
NOTE:
1. 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.
UNITS
ns
ns
ns
ns
ns
ns
CS (NOTE 1)
(NOTE 2)
A0 - A9
R/W
(NOTE 3)
tAS
DI (NOTE 3)
tWC
tWL
tDS
tAH
tDH
(NOTE 3)
NOTES:
1. Chip-Select (CS) permitted to change from high to low level or remain low on a selected device.
2. Chip-Select (CS) permitted to change from low to high level or remain low.
3. Don’t care.
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
6-9
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet CDP1821C3.PDF ] | |
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