|
|
PDF UJA1061TW Data sheet ( Hoja de datos )
| Número de pieza | UJA1061TW | |
| Descripción | Fault-tolerant CAN/LIN fail-safe system basis chip | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de UJA1061TW (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
UJA1061
Fault-tolerant CAN/LIN fail-safe system basis chip
Rev. 06 — 9 March 2010
Product data sheet
1. General description
The UJA1061 fail-safe System Basis Chip (SBC) replaces basic discrete components that
are common in every Electronic Control Unit (ECU) with a Controller Area Network (CAN)
and a Local Interconnect Network (LIN) interface. The fail-safe SBC supports all
networking applications that control various power and sensor peripherals by using
fault-tolerant CAN as the main network interface and LIN as a local sub-bus. The fail-safe
SBC contains the following integrated devices:
• ISO11898-3 compliant fault-tolerant CAN transceiver, interoperable with TJA1054,
TJA1054A and TJA1055
• LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3
• Advanced independent watchdog
• Dedicated voltage regulators for microcontroller and CAN transceiver
• Serial peripheral interface (full duplex)
• Local wake-up input port
• Inhibit/limp-home output port
In addition to the advantages of integrating these common ECU functions in a single
package, the fail-safe SBC offers an intelligent combination of system-specific functions
such as:
• Advanced low-power concept
• Safe and controlled system start-up behavior
• Advanced fail-safe system behavior that prevents any conceivable deadlock
• Detailed status reporting on system and subsystem levels
The UJA1061 is designed to be used in combination with a microcontroller that
incorporates a CAN controller. The fail-safe SBC ensures that the microcontroller is
always started up in a defined manner. In failure situations, the fail-safe SBC will maintain
microcontroller functionality for as long as possible to provide full monitoring and a
software-driven fall-back operation.
The UJA1061 is designed for 14 V single power supply architectures and for 14 V and
42 V dual power supply architectures.
1 page  
NXP Semiconductors
5. Pinning information
5.1 Pinning
UJA1061
Fault-tolerant CAN/LIN fail-safe system basis chip
n.c. 1
n.c. 2
TXDL 3
V1 4
RXDL 5
RSTN 6
INTN 7
EN 8
SDI 9
SDO 10
SCK 11
SCS 12
TXDC 13
RXDC 14
n.c. 15
TEST 16
Fig 2. Pin configuration
UJA1061
32 BAT42
31 RESERVED
30 V3
29 SYSINH
28 n.c.
27 BAT14
26 RTLIN
25 LIN
24 RTH
23 GND
22 CANL
21 CANH
20 V2
19 RTL
18 WAKE
17 INH/LIMP
001aad604
5.2 Pin description
UJA1061_6
Product data sheet
Table 2.
Symbol
n.c.
n.c.
TXDL
V1
RXDL
RSTN
INTN
EN
SDI
SDO
SCK
SCS
TXDC
RXDC
n.c.
TEST
Pin description
Pin Description
1 not connected
2 not connected
3 LIN transmit data input (LOW for dominant, HIGH for recessive)
4 voltage regulator output for the microcontroller (3.3 V or 5 V depending on
the SBC version)
5 LIN receive data output (LOW when dominant, HIGH when recessive)
6 reset output to microcontroller (active LOW; will detect clamping situations)
7 interrupt output to microcontroller (active LOW; open-drain, wire-AND this pin
to other ECU interrupt outputs)
8 enable output (active HIGH; push-pull, LOW with every reset / watchdog
overflow)
9 SPI data input
10 SPI data output (floating when pin SCS is HIGH)
11 SPI clock input
12 SPI chip select input (active LOW)
13 CAN transmit data input (LOW for dominant; HIGH for recessive)
14 CAN receive data output (LOW when dominant; HIGH when recessive)
15 not connected
16 test pin (should be connected to ground in application)
All information provided in this document is subject to legal disclaimers.
Rev. 06 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
5 of 77
5 Page 
NXP Semiconductors
UJA1061
Fault-tolerant CAN/LIN fail-safe system basis chip
When an interrupt event occurs the application software has to read the Interrupt register
within tRSTN(INT). Otherwise a fail-safe system reset is forced and Start-up mode will be
entered. If the application has read out the Interrupt register within the specified time, it
can decide whether to switch into Normal mode via an SPI access or to stay in Standby
mode.
The following operations are possible from Standby mode:
• Cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the
microcontroller is triggered periodically and checked for the correct response)
• Cyclic wake-up by the watchdog via a reset signal (a reset is performed periodically;
the SBC provides information about the reset source to allow different start
sequences after reset)
• Wake-up by activity on the CAN-bus or LIN-bus via an interrupt signal to the
microcontroller
• Wake-up by bus activity on the CAN-bus or LIN-bus via a reset signal
• Wake-up by increasing the microcontroller supply current without a reset signal
(where a stable supply is needed for the microcontroller RAM contents to remain valid
and wake-up from an external application not connected to the SBC)
• Wake-up by increasing the microcontroller supply current with a reset signal
• Wake-up due to a falling edge at pin WAKE forcing an interrupt to the microcontroller
• Wake-up due to a falling edge at pin WAKE forcing a reset signal
6.2.6 Sleep mode
In Sleep mode the microcontroller power supply (V1) and the INH/LIMP controlled
external supplies are switched off entirely, resulting in minimum system power
consumption. In this mode, the watchdog runs in Time-out mode or is completely off.
Entering Sleep mode results in an immediate LOW level on pin RSTN, thus stopping any
operation of the microcontroller. The INH/LIMP output is floating in parallel and pin V1 is
disabled. Only pin SYSINH can remain active to support the V2 voltage supply; this
depends on the V2C bit. It is also possible for V3 to be On, Off or in Cyclic mode to supply
external wake-up switches.
If the watchdog is not disabled in software, it will continue to run and force a system reset
upon overflow of the programmed period time. The SBC enters Start-up mode and pin V1
becomes active again. This behavior can be used for a cyclic wake-up from Sleep mode.
Depending on the application, the following operations can be selected from Sleep mode:
• Cyclic wake-up by the watchdog (only in Time-out mode); a reset is performed
periodically, the SBC provides information about the reset source to allow different
start sequences after reset
• Wake-up by activity on the CAN-bus, LIN-bus or falling edge at pin WAKE
• An overload on V3, only if V3 is in a cyclic or in continuously on mode
UJA1061_6
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 06 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
11 of 77
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UJA1061TW.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| UJA1061TW | Fault-tolerant CAN/LIN fail-safe system basis chip | NXP Semiconductors |
| UJA1061TW | Low speed CAN/LIN system basis chip |  Philips |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |