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PDF HV5530PG-G Data sheet ( Hoja de datos )
| Número de pieza | HV5530PG-G | |
| Descripción | 32-Channel Serial to Parallel Converter | |
| Fabricantes | Supertex | |
| Logotipo |  |
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Supertex inc.
32-Channel Serial to Parallel Converter
With Open Drain Outputs
HV5530
Features
►►Processed with HVCMOS® technology
►►Sink current minimum 100mA
►►Shift register speed 8.0MHz
►►Polarity and Blanking inputs
►►CMOS compatible inputs
►►Forward and reverse shifting options
►►Diode to VPP allows efficient power recovery
General Description
The HV5530 is a low-voltage serial to high-voltage parallel
converter with open drain outputs. This device has been designed
for use as a driver for AC-electroluminescent displays. It can also
be used in any application requiring multiple output high voltage
current sinking capabilities such as driving inkjet and electrostatic
print heads, plasma panels, vacuum fluorescent, or large matrix
LCD displays.
This device consists of a 32-bit shift register, 32 latches, and
control logic to perform the polarity select and blanking of the
outputs. Data is shifted through the shift register on the high to low
transition of the clock. The HV5530 shifts in the counter clockwise
direction when viewed from the top of the package. A data output
buffer is provided for cascading devices. This output reflects the
current status of the last bit of the shift register. Operation of the
shift register is not affected by the LE (latch enable), BL (blanking),
or the POL (polarity) inputs. Transfer of data from the shift register
to the latch occurs when the LE (latch enable) input is high. The
data in the latch is stored when LE is low.
Functional Block Diagram
POL
BL
LE
DATA
IN
CLK
32-Bit
Shift
Register
DATA
OUT
Latch
Latch
Latch
Latch
HVOUT1
HVOUT2
(Outputs 3 to 30 not shown)
HVOUT31
HVOUT32
Doc.# DSFP-HV5530
C072313
Supertex inc.
www.supertex.com
1 page  
HV5530
44-Lead PQFP Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
HVOUT11
HVOUT12
HVOUT13
HVOUT14
HVOUT15
HVOUT16
HVOUT17
HVOUT18
HVOUT19
HVOUT20
HVOUT21
HVOUT22
HVOUT23
HVOUT24
HVOUT25
HVOUT26
HVOUT27
HVOUT28
HVOUT29
HVOUT30
HVOUT31
HVOUT32
DATA OUTPUT
N/C
N/C
N/C
POL
CLK
VSS
VDD
LE
DATA INPUT
BL
N/C
HVOUT1
HVOUT2
HVOUT3
HVOUT4
HVOUT5
HVOUT6
HVOUT7
HVOUT8
HVOUT9
HVOUT10
Description
High voltage outputs.
Data output pin.
No connect.
Inverts the polarity of the HVOUT pins
Clock pin, shift registers shifts data on falling edge of input clock.
Reference voltage, usually ground.
Logic supply voltage.
Latch enable pin, data is shifted from shift register to latches on logic input high.
Data input pin.
Blanking pin sets all HVout pins low or high depending upon state of polarity.
See function table.
No connect.
High voltage outputs.
Doc.# DSFP-HV5530
C072313
Supertex inc.
5 www.supertex.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet HV5530PG-G.PDF ] | |
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