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PDF HV574PG-G Data sheet ( Hoja de datos )

Número de pieza HV574PG-G
Descripción 80-Channel Serial to Parallel Converter
Fabricantes Supertex 
Logotipo Supertex Logotipo



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No Preview Available ! HV574PG-G Hoja de datos, Descripción, Manual

Supertex inc.
HV574
100MHz, 80-Channel Serial to Parallel Converter
with Push-Pull Outputs
Features
►HVCMOS® technology
►5.0V CMS Logic
►Output voltage up to 80V
►Low power level shifting
►100MHz equivalent data rate using four
dynamic shift registers
►Latched data outputs
►Foreward and reverse shifting options (DIR pin)
Diode to VPP allows efficient power recovery
►Outputs may be hot switched
General Description
The HV574 is a low-voltage serial to high-voltage parallel con-verter
with push-pull outputs. This device has been designed for use as a
driver for printer applications. It can also be used in any application
requiring multiple output high-voltage current sour-cing and sinking
capability such as driving plasma panels, vacuum fluorescent
displays, or large matrix LCD displays.
The device has 4 parallel 20-bit dynamic shift registers, permitting
data rates 4X the speed of one (they are clocked together). There
are 80 static latches and control logic to perform the polarity select
and blanking of the outputs. HVOUT1 is connected to the first stage of
the first shift register through the polarity and blanking logic. Data is
shifted through the shift registers on the logic low to high transition
of the clock. The DIR pin causes CCW shifting when connected to
GND, and CW shifting when connected to VDD. A data output buffer
is provided for cascading devices. This output reflects the current
status of the last bit of the shift register (HVOUT80). Operation of the
shift register is not affected by the LE (latch enable), BL (blanking),
or the POL (polarity) inputs. Transfer of data from the shift registers
to the latches occurs when the LE (latch enable) input is high. The
data in the latches is stored when LE is low.
Functional Block Diagram
VDD
LE BL
POL
VPP
DIR
DINA
DOUTA
CLK
DINB
DOUTB
20-bit
Shift
Register
20-bit
Shift
Register
HVOUT1
HVOUT20
HVOUT21
HVOUT40
DINC
DOUTC
20-bit
Shift
Register
HVOUT41
HVOUT60
DIND
DOUTD
20-bit
Shift
Register
HVOUT61
HVOUT80
Doc.# DSFP-HV574
A061913
GND
Supertex inc.
www.supertex.com

1 page




HV574PG-G pdf
Function Table
Function
Data
HV574
CLK
Inputs
LE BL
POL
Outputs
DIR Shift Reg HV Outputs
Data Out
All O/P high
X
XXL LX
-
H
All O/P low
X
XX LHX
-
L
O/P normal
X
XXHHX
- No inversion
O/P inverted
X
XXH L X
-
Inversion
Data falls
through
(latches
transparent)
L
H
L
H
HHHX
HHHX
HH LX
HH LX
L
H
L
H
L
H
H
L
Data stored/
latches loaded
X
X
X LHHX
XLHLX
* Stored Data
*
Inversion of
stored data
DINX
H
H
H
H
Qn→Qn+1
New H or L
I/O relation
DINX
L
H H H Qn→Qn+1 Previous H or L
DOUTX
L
HH
L Qn→Qn-1 Previous H or L
DOUTX
H
H
H
L
Qn→Qn-1
New H or L
Note:
* = dependent on previous stage’s state. See Pin configuration for DIN and DOUT pin designation for CW and CCW shift.
-
-
-
-
-
-
-
-
-
-
DOUTX
DOUTX
DINX
DINX
Doc.# DSFP-HV574
A061913
Supertex inc.
5 www.supertex.com

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