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PDF UT54ACS165E Data sheet ( Hoja de datos )
| Número de pieza | UT54ACS165E | |
| Descripción | 8-Bit Parallel Shift Registers | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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UT54ACS165E
8-Bit Parallel Shift Registers
October 2008
www.aeroflex.com/Logic
FEATURES
• Complementary outputs
• Direct overriding load (data) inputs
• Gated clock inputs
• Parallel-to-serial data conversions
• 0.6μm CRH CMOS Process
- Latchup immune
• High speed
• Low power consumption
• Wide operating power supply from 3.0V to 5.5V
• Available QML Q or V processes
• 16-lead flatpack
DESCRIPTION
The UT54ACS165E is an 8-bit serial shift register that, when clocked,
shifts the data toward serial output QH. Parallel-in access to each stage
is provided by eight individual data inputs that are enabled by a low
level at the SH/LD input. The devices feature a clock inhibit function
and a complemented serial output QH .
Clocking is accomplished by a low-to-high transition of the CLK input
while SH/LD is held high and CLK INH is held low. The functions of
the CLK and CLK INH (clock inhibit) inputs are interchangeable.
Since a low CLK input and a low-to-high transition of CLK INH will
also accomplish clocking, CLK INH should be changed to the high
level only while the CLK input is high. Parallel loading is disabled
when SH/LD is held high. Parallel inputs to the registers are enabled
while SH/LD is low independently of the levels of CLK, CLK INH or
SER inputs.
The device is characterized over the full HiRel temperature range of
-55°C to +125°C.
PINOUT
SH/LD
CLK
E
F
G
H
QH
VSS
16-Lead Flatpack
Top View
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
CLK INH
D
C
B
A
SER
QH
FUNCTION TABLE
INPUTS
INTERNAL OUTPUTS
OUTPUTS
SH/ CLK CLK SER PARALLEL
LD INH
A . . . H QA QB QH QH
L X X X a ... h a b h h
H L L X X QA QB QH QH
H L ↑ H X H QA QG QG
H L ↑ L X L QA QG QG
H H X X X QA QB QH QH
Note:
1. Qn = The state of the referenced output one setup time prior to the Low-to-
High clock transition.
LOGIC SYMBOL
(1)
SH/LD
(15)
CLK INH
CLK (2)
SRG8
C1 (LOAD)
≥1 C2/
SER (10)
A (11)
2D
1D
B (12)
C (13)
D (14)
E (3)
F (4)
G (5)
H (6)
1D
1D
(9)
(7) QH
QH
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
1
1 page  
AC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS165E2
(VDD = 3.0V to 5.5V; VSS = 0V 1, -55°C < TC < +125°C)
SYMBOL
PARAMETER
CONDITION
VDD
tPLH1
CLK or CLKINH to QH or QH CL = 30pF
3.0V & 3.6V
4.5V & 5.5V
CL = 50pF
3.0V & 3.6V
4.5V & 5.5V
tPHL1
CLK or CLKINH to QH or QH CL = 30pF
3.0V & 3.6V
4.5V & 5.5V
CL = 50pF
3.0V & 3.6V
4.5V & 5.5V
tPLH2
SH/LD to QH or QH
CL = 30pF
3.0V & 3.6V
4.5V & 5.5V
CL = 50pF
3.0V & 3.6V
4.5V & 5.5V
tPHL2
SH/LD to QH or QH
CL = 30pF
3.0V & 3.6V
4.5V & 5.5V
CL = 50pF
3.0V & 3.6V
4.5V & 5.5V
tPLH3
H to QH
CL = 30pF
3.0V & 3.6V
4.5V & 5.5V
CL = 50pF
3.0V & 3.6V
4.5V & 5.5V
tPHL3
H to QH
CL = 30pF
3.0V & 3.6V
4.5V & 5.5V
CL = 50pF
3.0V & 3.6V
4.5V & 5.5V
tPLH4
H to QH
CL = 30pF
3.0V & 3.6V
4.5V & 5.5V
CL = 50pF
3.0V & 3.6V
4.5V & 5.5V
tPLH4
H to QH
CL = 30pF
3.0V & 3.6V
4.5V & 5.5V
CL = 50pF
3.0V & 3.6V
4.5V & 5.5V
5
MINIMUM MAXIMUM UNIT
2 18 ns
2 14
2 22 ns
2 18
2 21 ns
2 17
2 25 ns
2 21
2 18 ns
2 14
2 22 ns
2 18
2 21 ns
2 17
2 25 ns
2 21
2 17 ns
2 13
2 21 ns
2 17
2 21 ns
2 17
2 25 ns
2 21
2 18 ns
2 14
2 22 ns
2 18
2 20 ns
2 16
2 24 ns
2 20
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet UT54ACS165E.PDF ] | |
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