|
|
PDF CY62146GSL Data sheet ( Hoja de datos )
| Número de pieza | CY62146GSL | |
| Descripción | 4-Mbit (256K words x 16 bit) Static RAM | |
| Fabricantes | Cypress | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY62146GSL (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
4-Mbit (256K words × 16 bit) Static RAM with
Error-Correcting Code (ECC)
4-Mbit (256K words × 16 bit) Static RAM with Error-Correcting Code (ECC)
Features
■ High speed: 45 ns/55 ns
■ Ultra-low standby power
❐ Typical standby current: 3.5 A
❐ Maximum standby current: 8.7 A
■ Embedded ECC for single-bit error correction[1]
■ Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V
■ 1.0-V data retention
■ TTL-compatible inputs and outputs
■ Error indication (ERR) pin to indicate 1-bit error detection and
correction
■ Pb-free 48-ball VFBGA and 44-pin TSOP II packages
Functional Description
CY62146G/ CY62146GE and CY62146GSL / CY62146GESL
are high-performance CMOS low-power (MoBL) SRAM devices
with embedded ECC. Both devices are offered in single and dual
chip enable options and in multiple pin configurations. The
CY62146GE/ CY62146GESL device includes an ERR pin that
signals an error-detection and correction event during a read
cycle. The CY62146GSL/CY62146GESL[1] device supports a
wide voltage range of 2.2 V–3.6 V and 4.5 V–5.5 V.
Devices with a single chip enable input are accessed by
asserting the chip enable (CE) input LOW. Dual chip enable
devices are accessed by asserting both chip enable inputs – CE1
as low and CE2 as HIGH.
Data writes are performed by asserting the Write Enable (WE)
input LOW, while providing the data on I/O0 through I/O15 and
address on A0 through A17 pins. The Byte High Enable (BHE)
and Byte Low Enable (BLE) inputs control write operations to the
upper and lower bytes of the specified memory location. BHE
controls I/O8 through I/O15 and BLE controls I/O0 through I/O7.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on the I/O lines (I/O0 through I/O15).
Byte accesses can be performed by asserting the required byte
enable signal (BHE or BLE) to read either the upper byte or the
lower byte of data from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the
device is deselected (CE HIGH for a single chip enable device
and CE1 HIGH/CE2 LOW for a dual chip enable device), or
control signals are deasserted (OE, BLE, BHE).
On the CY62146GE/CY62146GESL devices, the detection and
correction of a single-bit error in the accessed location is
indicated by the assertion of the ERR output (ERR = HIGH)[2].
See the Truth Table –
CY62146G/CY62146GE/CY62146GSL/CY62146GESL
on
page 17 for a complete description of read and write modes.
The logic block diagrams are on page 2.
Product Portfolio
Product[3]
CY62146G(E)18
CY62146G(E)30
CY62146G(E)
CY62146G(E)SL[5]
Features and
Options
(see the Pin
Configurations
section)
Single or dual
Chip Enables
Optional ERR
pin
Range
Industrial
VCC Range (V) Speed (ns)
1.65 V–2.2 V
2.2 V–3.6 V
4.5 V–5.5 V
2.2 V–3.6 V and
4.5 V–5.5 V
55
45
Power Dissipation
Operating ICC, (mA)
f = fmax
Standby, ISB2 (µA)
Typ[4]
Max
Typ[4]
Max
15 20 3.5 10
15 20 3.5 8.7
Notes
1. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V.
2. This device does not support automatic write-back on error detection.
3. The ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information for details.
4.
Typical values
VCC = 3 V (for
are included for reference only and are not guaranteed or
VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range
tested. Typical values are measured
of 4.5 V–5.5 V), TA = 25 °C.
at
VCC
=
1.8
V
(for
a
VCC
range
of
1.65
V–2.2
V),
5. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-95420 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 11, 2016
1 page  
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Pin Configuration – CY62146G/CY62146GSL (continued)
Figure 3. 44-pin TSOP II Pinout (Single Chip Enable without ERR) – CY62146G/CY62146GSL [7]
A4
A3
A2
A1
A0
/ CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
/ WE
A17
A16
A15
A14
A13
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 36
10 35
11 34
12 44- TSOP-II 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
A5
A6
A7
/ OE
/ BHE
/ BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
Note
7. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
Document Number: 001-95420 Rev. *C
Page 5 of 22
5 Page 
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Data Retention Characteristics
Over the Operating range
Parameter
VDR
ICCDR[20, 21]
Description
VCC for data retention
Data retention current
tCDR[22, 23]
tR[23]
Chip deselect to data retention
time
Operation recovery time
Conditions
Vcc = 1.2 V
CE1 > VCC 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
Min
1
–
0
45/55
Typ [19]
–
–
–
Max Unit
–V
13 A
– ns
– ns
Data Retention Waveform
Figure 8. Data Retention Waveform
V CC
C E 1
V C C (m in )
tCDR
D A T A R E T E N T IO N M O D E
V DR = 1 .0 V
V C C (m in )
tR
CE2
Notes
19. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
20. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
21. ICCDR is guaranteed only after device is first powered up to VCC(min) and then brought down to VDR.
22. These parameters are guaranteed by design.
23. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-95420 Rev. *C
Page 11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CY62146GSL.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY62146GSL | 4-Mbit (256K words x 16 bit) Static RAM | Cypress |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |