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PDF CY62146GN Data sheet ( Hoja de datos )
| Número de pieza | CY62146GN | |
| Descripción | 4-Mbit (256K x 16) Static RAM | |
| Fabricantes | Cypress | |
| Logotipo |  |
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CY62146GN MoBL®
4-Mbit (256K × 16) Static RAM
4-Mbit (256K × 16) Static RAM
Features
■ Very high speed: 45 ns
■ Temperature ranges
❐ Industrial: –40 °C to +85 °C
■ Wide voltage range: 2.20 V to 3.60 V and 4.5 V to 5.5 V
■ Ultra low standby power
❐ Typical standby current: 3.5 A
❐ Maximum standby current: 8.7 A
■ Ultra low active power
❐ Typical active current: 3.5 mA at f = 1 MHz
■ Automatic power down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in a 44-pin TSOP II and 48-ball VFBGA Packages
Functional Description
The CY62146GN is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features an
advanced circuit design designed to provide an ultra low active
current. Ultra low active current is ideal for providing More
Battery Life (MoBL®) in portable applications such as cellular
telephones. The device also has an automatic power down
feature that significantly reduces power consumption by 80
percent when addresses are not toggling.The device can also be
put into standby mode reducing power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (I/O0 through I/O15) are placed in a high impedance
state when the device is deselected (CE HIGH), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or a write operation is in
progress (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from the I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
Logic Block Diagram
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
256K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-95417 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 18, 2016
1 page  
CY62146GN MoBL®
Capacitance
Parameter [9]
Description
CIN
COUT
Input capacitance
Output capacitance
Thermal Resistance
Parameter [9]
Description
JA Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
TA = 25 C, f = 1 MHz, VCC = VCC(typ)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
Max Unit
10 pF
10 pF
TSOP II
68.85
15.97
Unit
C/W
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [10]
VCC
Output
R1
30 pF
R2
VCC
10%
GND
Rise Time = 1 V/ns
All Input Pulses
90%
Including
JIG and
Scope
Equivalent to: Thevenin Equivalent
Output
RTH
V
90%
10%
Fall Time = 1 V/ns
Parameters
R1
R2
RTH
VTH
2.50 V
16667
15385
8000
1.20
3.0 V
1103
1554
645
1.75
Unit
V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
10. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-95417 Rev. *C
Page 5 of 17
5 Page 
CY62146GN MoBL®
Truth Table
CE [31]
H
WE
X
OE BHE BLE
Inputs/Outputs
X X X High-Z
L X X H H High-Z
L H L L L Data out (I/O0–I/O15)
L H L H L Data out (I/O0–I/O7);
I/O8–I/O15 in High-Z
L H L L H Data out (I/O8–I/O15);
I/O0–I/O7 in High-Z
L H H X X High-Z
L L X L L Data in (I/O0–I/O15)
L L X H L Data in (I/O0–I/O7);
I/O8–I/O15 in High-Z
L L X L H Data in (I/O8–I/O15);
I/O0–I/O7 in High-Z
Mode
Deselect/power-down
Output disabled
Read
Read
Read
Output disabled
Write
Write
Write
Power
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Note
31. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
Document Number: 001-95417 Rev. *C
Page 11 of 17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet CY62146GN.PDF ] | |
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