CY62162GE Datasheet PDF - Cypress
| Part Number | CY62162GE | |
| Description | 16-Mbit (512K x 32) Static RAM | |
| Manufacturers | Cypress | |
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CY62162G/CY62162GE MoBL®
16-Mbit (512 K × 32) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (512 K × 32) Static RAM with Error-Correcting Code (ECC)
Features
■ Ultra-low standby power
❐ Typical standby current: 5.5 μA
❐ Maximum standby current: 16 μA
■ High speed: 45 ns / 55 ns
■ Embedded error-correcting code (ECC) for single-bit error
correction
■ Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V
■ 1.0-V data retention
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ ERR pin to indicate 1-bit error detection and correction
■ Easy memory expansion with CE1 and CE2 features
■ Available in Pb-free 119-ball PBGA package, 512 K × 32 bits
SRAM
Functional Description
The CY62162G and CY62162GE devices are high performance
CMOS MoBL SRAM organized as 512K words by 32-bits. Both
CY62162G and CY62162GE are available with dual chip
enables. CY62162GE includes an error indication pin that
signals the host processor in the case of a single bit
error-detection and correction event. It is ideal for providing More
Battery Life™ (MoBL®) in portable applications such as cellular
telephones. The device also has an automatic power down
feature that reduces power consumption when addresses are
not toggling. Placing the device into standby mode reduces
power consumption by more than 99% when deselected (CE1
HIGH or CE2 LOW or BA-D HIGH). The input and output pins
(I/O0 through I/O31) are placed in a high impedance state when
deselected (CE1 HIGH or CE2 LOW) or outputs are disabled (OE
HIGH) or the byte selects are disabled (BA-D HIGH).
To write to the device, take chip enables (CE1 LOW, CE2 HIGH)
and write enable (WE) input LOW. If byte enable A (BA) is LOW,
then data from I/O pins (I/O0 through I/O7) is written into the
location specified on the address pins (A0 through A18). If byte
enable B (BB) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A18). Likewise, BC and BD correspond with the I/O
pins I/O16 to I/O23 and I/O24 to I/O31, respectively.
To read from the device, take chip enables (CE1 LOW, CE2
HIGH), and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If the first byte enable (BA) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If byte enable (BB) is LOW, then data from
memory appears on I/O8 to I/O15. Likewise, BC and BD
correspond to the third and fourth bytes. During Read operation,
in case of a single bit error detection and correction, ERR is
asserted HIGH[1]. See the Truth Table – CY62162G /
CY62162GE on page 15 for a complete description of read and
write modes.
CY62162G and CY62162GE devices are available in a 119-ball
PBGA package with center power and ground pinout.
Note
1. This device does not support automatic write-back on error detection.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-81598 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 31, 2015
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CY62162G/CY62162GE MoBL®
Pin Configurations
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Figure 1. 119-ball FBGA pinout [2]
CY62162G (512 K × 32)
1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
NC
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
2
A4
A18
Bc
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
A14
A12
A8
3
A3
A17
CE2
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
Bd
A11
A7
4
A2
CE1
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
WE
OE
5
A1
A16
NC
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
Bb
A10
A6
Figure 2. 119-ball FBGA pinout [2, 3]
CY62162GE (512 K × 32)
1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
ERR
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
2
A4
A18
Bc
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
A14
A12
A8
3
A3
A17
CE2
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
Bd
A11
A7
4
A2
CE1
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
WE
OE
5
A1
A16
NC
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
Bb
A10
A6
6
A0
A15
Ba
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
A13
A9
A5
7
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
NC
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
6
A0
A15
Ba
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
A13
A9
A5
7
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
NC
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
Note
2. NC pins are not connected internally to the die.
3. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 001-81598 Rev. *C
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Featured Datasheets
| Part Number | Description | MFRS |
| CY62162G | The function is 16-Mbit (512K x 32) Static RAM. Cypress | |
| CY62162GE | The function is 16-Mbit (512K x 32) Static RAM. Cypress | |
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