|
|
PDF CY62167G Data sheet ( Hoja de datos )
| Número de pieza | CY62167G | |
| Descripción | 16-Mbit (1M Words x 16 Bit) Static RAM | |
| Fabricantes | Cypress | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY62167G (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
|
No Preview Available !
CY62167G Automotive
16-Mbit (1M Words × 16 Bit) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC)
Features
■ Ultra-low standby power
❐ Typical standby current: 5.5 A
❐ Maximum standby current: 75 A
■ High speed: 45 ns / 55 ns
■ Embedded error-correcting code (ECC) for single-bit error
correction
■ Temperature Ranges:
❐ Automotive-A: -40 C to +85 C
❐ Automotive-E: -40 C to +125 C
■ Operating voltage range: 2.2 V to 3.6 V
■ 1.0-V data retention
■ TTL-compatible inputs and outputs
■ Available in Pb-free 48-ball VFBGA and 48-pin TSOP I
packages
Functional Description
CY62167G is high-performance CMOS low-power (MoBL)
SRAM devices with embedded ECC. This device is offered in
dual chip-enable.
Devices with dual chip-enable are accessed by asserting both
chip-enable inputs – CE1 as LOW and CE2 as HIGH.
Data writes are performed by asserting the Write Enable input
(WE) LOW, and providing the data and address on device data
(I/O0 through I/O15) and address (A0 through A19) pins
respectively. The Byte High/Low Enable (BHE, BLE) inputs
control byte writes, and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O8 through
I/O15; BLE controls I/O0 through I/O7.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on I/O lines (I/O0 through I/O15). Byte
accesses can be performed by asserting the required byte
enable signal (BHE, BLE) to read either the upper byte or the
lower byte of data from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the
device is deselected (CE1 HIGH / CE2 LOW for dual chip-enable
device), or control signals are de-asserted (OE, BLE, and BHE).
These devices also have a unique “Byte Power down” feature
where if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switches to standby mode irrespective of the
state of the chip enable(s), thereby saving power.
The CY62167G device is available in a Pb-free 48-ball VFBGA
and 48-pin TSOP I packages. The device in the 48-pin TSOP I
package can also be configured to function as a 2 M words × 8
bit device.The logic block diagram is on page 2. Refer to Pin
Configurations on page 4 and the associated footnotes for
details.
Note
1. This device does not support automatic write-back on error detection.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-84902 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 12, 2016
1 page  
CY62167G Automotive
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Supply voltage
to ground potential [5] .......................... –0.5 V to VCC + 0.5 V
DC voltage applied to outputs
in HI-Z state [5] .................................... –0.5 V to VCC + 0.5 V
DC input voltage [5] ............................. –0.5 V to VCC + 0.5 V
DC Electrical Characteristics
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch-up current ..................................................... >140 mA
Operating Range
Grade
Automotive-E
Automotive-A
Ambient Temperature
–40 C to +125 C
–40 C to +85 C
VCC
2.2 V to 3.6 V
Over the Operating Range
Parameter
Description
Test Conditions
55 ns (Automotive -E)
Min Typ [6] Max
55 ns (Automotive-A)
Min Typ [6] Max
Unit
VOH Output HIGH 2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA
voltage
2.7 V to 3.6 V VCC = Min, IOH = –1.0 mA
VOL Output LOW 2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA
voltage
2.7 V to 3.6 V VCC = Min, IOL = 2.1 mA
VIH
Input HIGH 2.2 V to 2.7 V –
voltage[5]
2.7 V to 3.6 V –
VIL
Input LOW
voltage[5]
2.2 V to 2.7 V –
2.7 V to 3.6 V –
2.0 –
– 2.0 –
–V
2.2 –
– 2.2 –
–
––
0.4 – –
0.4 V
––
0.4 – –
0.4
2.0
2.0
–0.3
– VCC + 0.3 2.0
– VCC + 0.3 2.0
– 0.6 –0.3
– VCC + 0.3 V
– VCC + 0.3
– 0.6 V
–0.3 –
0.8 –0.3 –
0.8
IIX
Input leakage current
GND < VIN < VCC
–4.0 –
+4.0 –1.0 –
+1.0 A
IOZ
Output leakage current
GND < VOUT < VCC, Output
disabled
–4.0 –
+4.0 –1.0 –
+1.0 A
ICC
ISB1[7]
ISB2[7]
VCC operating supply
current
Automatic power down
current – CMOS inputs;
VCC = 2.2 to 3.6 V
Automatic power down
current – CMOS inputs;
VCC = 2.2 to 3.6 V
VCC = Max,
IOUT = 0 mA,
CMOS levels
f = fMAX
f =1 MHz
CE1 > VCC – 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = VCC(max)
CE1 > VCC – 0.2V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = 0, VCC = VCC(max)
–
–
–
–
29.0
7.0
5.5
5.5
40.0
18.0
75.0
75.0
– 29.0
– 7.0
– 5.5
36.0 mA
9.0 mA
16.0 A
– 5.5 16.0 A
Notes
5. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 2 ns.
6. Indicates the value for the center of Distribution at 3.0 V, 25 °C and not 100% tested.
7. Chip enables (CE1 and CE2) and BHE, BLE and BYTE must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 001-84902 Rev. *D
Page 5 of 19
5 Page 
CY62167G Automotive
Switching Waveforms (continued)
Figure 8. Write Cycle No. 2 (CE Controlled) [25, 26, 27]
ADDRESS
CE
WE
tWC
tSA
tAW
tSCE
tPWE
tHA
BHE/
BLE
tBW
OE
DATA I/O
tHZOE
tSD tHD
DATAIN VALID
Notes
25.
For
CE
all dual chip
is HIGH.
enable
devices,
CE
is
the
logical
combination
of
CE1
and
CE2.
When
CE1
is
LOW
and
CE2
is
HIGH,
CE
is
LOW;
when
CE1
is
HIGH
or
CE2
is
LOW,
26.
The internal write
a write and any of
time of the memory is defined
these signals can terminate a
by the overlap
write by going
IoNf AWCET=IVVEI.L,TCheE1da=taVIiLn,pBuHt sEeoturpBaLnEdohroblodtthim=inVgILm, aunsdt
rCeEfe2r
=toVtIhHe.
All signals must be ACTIVE to initiate
edge of the signal that terminates the
write.
27. Data I/O is in high impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
Document Number: 001-84902 Rev. *D
Page 11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet CY62167G.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY62167DV18 | 16M (1024K x 16) Static RAM |  Cypress Semiconductor |
| CY62167DV20 | 16-Mb (1024K x 16) Static RAM | Cypress Semiconductor |
| CY62167DV30 | 16-Mbit (1M x 16) Static RAM | Cypress Semiconductor |
| CY62167E | 16-Mbit (1M x 16 / 2M x 8) Static RAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |