PDF CY7C1381D Data sheet ( Hoja de datos )

Número de pieza	CY7C1381D
Descripción	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Fabricantes	Cypress
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No Preview Available ! CY7C1381D CY7C1383D CY7C1383F 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM Features ■ Supports 133 MHz bus operations ■ 512K × 36 and 1M × 18 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O supply (VDDQ) ■ Fast clock-to-output time ❐ 6.5 ns (133 MHz version) ■ Provides high performance 2-1-1-1 access rate ■ User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed write ■ Asynchronous output enable ■ CY7C1381D available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package. CY7C1383D available in JEDEC-standard Pb-free 100-pin TQFP. CY7C1383F available in non Pb-free 165-ball FBGA package. ■ IEEE 1149.1 JTAG-Compatible Boundary Scan ■ ZZ sleep mode option Functional Description The CY7C1381D/CY7C1383D/CY7C1383F is a 3.3 V, 512K × 36 and 1M × 18 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWx, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. The CY7C1381D/CY7C1383D/CY7C1383F allows interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). CY7C1381D/CY7C1383D/CY7C1383F operates from a +3.3 V core power supply while all outputs operate with a +2.5 V or +3.3 V supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible. For a complete list of related documentation, click here. Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Description 133 MHz 6.5 210 70 100 MHz 8.5 175 70 Unit ns mA mA Errata: For information on silicon errata, see “Errata” on page 32. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation • 198 Champion Court Document Number: 38-05544 Rev. U • San Jose, CA 95134-1709 • 408-943-2600 Revised March 25, 2016 1 page CY7C1381D CY7C1383D CY7C1383F Pin Configurations (continued) Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout(3 Chip Enable) [3, 4] 123 A NC/288M A CE1 B NC/144M A C DQPC NC D DQC DQC CE2 VDDQ VDDQ E DQC DQC VDDQ F DQC DQC VDDQ G DQC DQC VDDQ H NC NC NC J DQD DQD VDDQ K DQD DQD VDDQ L DQD DQD VDDQ M DQD DQD VDDQ N DQPD NC VDDQ P NC NC/72M A R MODE NC/36M A CY7C1381D (512K × 36) 4 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 11 A NC A NC/576M NC/1G DQB DQB DQB DQB NC DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA NC A DQA DQA DQA DQA DQPA A AA 123 A NC/288M A CE1 B NC/144M A C NC NC D NC DQB CE2 VDDQ VDDQ E NC DQB VDDQ F NC DQB VDDQ G NC DQB VDDQ H VSS NC NC J DQB NC VDDQ K DQB NC VDDQ L DQB NC VDDQ M DQB NC VDDQ N DQPB NC VDDQ P NC NC/72M A R MODE NC/36M A CY7C1383F (1M × 18) 4 BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 11 AA A NC/576M NC/1G NC NC NC NC NC DQPA DQA DQA DQA DQA ZZ DQA DQA DQA DQA NC NC NC NC NC NC AA AA Notes 3. Errata: The ZZ ball (H11) needs to be externally connected to ground. For more information, see “Errata” on page 32. 4. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata” on page 32. Document Number: 38-05544 Rev. U Page 5 of 37 5 Page CY7C1381D CY7C1383D CY7C1383F Truth Table for Read/Write The truth table for CY7C1381D read/write follows. [12, 13] Function (CY7C1381D) Read Read Write Byte A (DQA, DQPA) Write Byte B(DQB, DQPB) Write Bytes A, B (DQA, DQB, DQPA, DQPB) Write Byte C (DQC, DQPC) Write Bytes C, A (DQC, DQA, DQPC, DQPA) Write Bytes C, B (DQC, DQB, DQPC, DQPB) Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB, DQPA) Write Byte D (DQD, DQPD) Write Bytes D, A (DQD, DQA, DQPD, DQPA) Write Bytes D, B (DQD, DQA, DQPD, DQPA) Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) Write Bytes D, B (DQD, DQB, DQPD, DQPB) Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC, DQPA) GW H H H H H H H H H H H H H H H BWE H L L L L L L L L L L L L L L Truth Table for Read/Write The truth table for CY7C1383D/CY7C1383F read/write follows. [12, 13] Function (CY7C1383D/CY7C1383F) GW BWE Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) Write All Bytes Write All Bytes Read Read Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) Write All Bytes Write All Bytes H H L H H H H H L L L X H L L L L X BWD X H H H H H H H H L L L L L L BWC X H H H H L L L L H H H H L L BWB L L X X H H L L X BWB X H H L L H H L L H H L L H H BWA X H L H L H L H L H L H L H L BWA L L X X H L H L X Notes 12. X=Don't Care, H = Logic HIGH, L = Logic LOW. 13. The table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active. Document Number: 38-05544 Rev. *U Page 11 of 37 11 Page

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