CY7C1460SV25 Datasheet PDF - Cypress
| Part Number | CY7C1460SV25 | |
| Description | 36-Mbit (1M x 36/2M x 18) Pipelined SRAM | |
| Manufacturers | Cypress | |
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CY7C1460SV25
CY7C1462SV25
36-Mbit (1M × 36/2M × 18)
Pipelined SRAM with NoBL™ Architecture
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture
Features
■ Pin compatible and functionally equivalent to ZBT™
■ Supports 250-MHz bus operations with zero wait states
❐ Available speed grades are 250 and 167 MHz
■ Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte Write capability
■ 2.5-V core power supply
■ 2.5-V I/O power supply
■ Fast clock-to-output times
❐ 2.6 ns (for 250-MHz device)
■ Clock Enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ CY7C1460SV25 available in JEDEC-standard Pb-free 100-pin
TQFP package and non Pb-free 165-ball FBGA package.
CY7C1462SV25 available in Pb-free 100-pin TQFP package
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ Burst capability – linear or interleaved burst order
■ “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1460SV25/CY7C1462SV25 are 2.5 V,
1M × 36/2M × 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL logic, respectively. They are
designed to support unlimited true back to back Read/Write
operations with no wait states. The
CY7C1460SV25/CY7C1462SV25 are equipped with the
advanced (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent Write/Read transitions.
CY7C1460SV25/CY7C1462SV25 are pin compatible and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1460SV25 and BWa–BWb for
CY7C1462SV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
250 MHz
2.6
435
120
167 MHz
3.4
335
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-43804 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 7, 2016
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CY7C1460SV25
CY7C1462SV25
Pin Configurations (continued)
Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
123
A NC/576M
B NC/1G
A
A
CE1
CE2
C DQPc NC VDDQ
D
DQc
DQc
VDDQ
E
DQc
DQc
VDDQ
F
DQc
DQc
VDDQ
G
DQc
DQc
VDDQ
H NC NC NC
J
DQd
DQd
VDDQ
K
DQd
DQd
VDDQ
L
DQd
DQd
VDDQ
M
DQd
DQd
VDDQ
N DQPd NC VDDQ
P NC/144M NC/72M A
R MODE
A
A
CY7C1460SV25 (1M × 36)
4 567
BWc
BWd
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
BWb
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1
CEN
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
A TMS A0 TCK
8
ADV/LD
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
A
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC/288M
A
Document Number: 001-43804 Rev. *J
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
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