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PDF CY7S1041G Data sheet ( Hoja de datos )
| Número de pieza | CY7S1041G | |
| Descripción | 4-Mbit (256K words x 16 bit) Static RAM | |
| Fabricantes | Cypress | |
| Logotipo |  |
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CY7S1041G
CY7S1041GE
4-Mbit (256K words × 16 bit) Static RAM
with PowerSnooze™ and Error Correcting Code (ECC)
4-Mbit (256K words × 16 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC)
Features
■ High speed
❐ Access time (tAA) = 10 ns / 15 ns
■ Ultra-low power Deep-Sleep (DS) current
❐ IDS = 15 µA
■ Low active and standby currents
❐ Active Current ICC = 38-mA typical
❐ Standby Current ISB2 = 6-mA typical
■ Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V,
4.5 V to 5.5 V
■ Embedded ECC for single-bit error correction[1]
■ 1.0-V data retention
■ TTL- compatible inputs and outputs
■ Error indication (ERR) pin to indicate 1-bit error detection and
correction
■ Available in Pb-free 44-pin TSOP II and 48-ball VFBGA
Functional Description
The CY7S1041G is a high-performance PowerSnooze™ static
RAM organized as 256K words × 16 bits. This device features
fast access times (10 ns) and a unique ultra-low power
Deep-Sleep mode. With Deep-Sleep mode currents as low as
15 µA, the CY7S1041G/ CY7S1041GE devices combine the
best features of fast and low- power SRAMs in industry-standard
package options. The device also features embedded ECC. logic
which can detect and correct single-bit errors in the accessed
location.
Deep-Sleep input (DS) must be deasserted HIGH for normal
operating mode.
To perform data writes, assert the Chip Enable (CE) and Write
Enable (WE) inputs LOW, and provide the data and address on
device data pins (I/O0 through I/O15) and address pins (A0
through A17) respectively. The Byte High Enable (BHE) and Byte
Low Enable (BLE) inputs control byte writes, and write data on
the corresponding I/O lines to the memory location specified.
BHE controls I/O8 through I/O15 and BLE controls I/O0 through
I/O7.
To perform data reads, assert the Chip Enable (CE) and Output
Enable (OE) inputs LOW and provide the required address on
the address lines. Read data is accessible on the I/O lines (I/O0
through I/O15). You can perform byte accesses by asserting the
required byte enable signal (BHE or BLE) to read either the
upper byte or the lower byte of data from the specified address
location
The device is placed in a low-power Deep-Sleep mode when the
Deep-Sleep input (DS) is asserted LOW. In this state, the device
is disabled for normal operation and is placed in a low power data
retention mode. The device can be activated by deasserting the
Deep-Sleep input (DS) to HIGH.
The CY7S1041G is available in 44-pin TSOP II, 48-ball VFBGA
and 44-pin (400-mil) Molded SOJ.
Product Portfolio
Product [2]
Range
CY7S1041G(E)18
CY7S1041G(E)30
CY7S1041G(E)
Industrial
VCC Range (V)
1.65 V–2.2 V
2.2 V–3.6 V
4.5–5.5 V
Speed
(ns)
15
10
10
Power Dissipation
Operating
(mA)
ICC,
f = fmax
Typ [3] Max
Standby,
(mA)
ISB2
Typ [3] Max
Deep-Sleep
current (µA)
Typ [3] Max
– 40 6 8 – 15
38 45
38 45
Notes
1. This device does not support automatic write back on error detection.
2. ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information for details.
3.
Typical values
VCC = 3 V (for
are included for reference only and are
VCC range of 2.2 V – 3.6 V), and VCC =
not guaranteed or tested.
5 V (for VCC range of 4.5
Typical
V – 5.5
values are measured
V), TA = 25 °C.
at
VCC
=
1.8
V
(for
VCC
range
of
1.65
V
–
2.2
V),
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-92576 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 19, 2015
1 page  
CY7S1041G
CY7S1041GE
Pin Configurations (continued)
Figure 4. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable Figure 5. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable
without ERR, CY7S1041G [7], Package/Grade ID: BVXI [9] with ERR, CY7S1041GE [7, 8], Package/Grade ID: BVXI [9]
1 2 34 5 6
BLE OE A0 A1 A2 DS
I/O0 BHE A3
A4 CE I/O8
I/O1 I/O2 A5
A6 I/O10 I/O9
VSS I/O3 A17
A7 I/O11 VCC
A
B
C
D
1 2 34 5 6
BLE OE A0 A1 A2 DS
I/O0 BHE A3
A4 CE I/O8
I/O1 I/O2 A5
A6 I/O10 I/O9
VSS I/O3 A17
A7 I/O11 VCC
A
B
C
D
VCC I/O4 NC A16 I/O12 VSS
E
VCC I/O4 ERR A16 I/O12 VSS
E
I/O6 I/O5 A14 A15 I/O13 I/O14
I/O7 NC A12 A13 WE I/O15
NC A8 A9 A10 A11 NC
F
G
H
I/O6 I/O5 A14 A15 I/O13 I/O14
I/O7 NC A12 A13 WE I/O15
NC A8 A9 A10 A11 NC
F
G
H
Notes
7. NC pins are not connected internally to the die.
8. ERR is an output pin.
9.
Package
balls are
type BVJXI
swapped.
is
JEDEC
compliant
compared
to
package
type
BVXI.
The
difference
between
the
two
is
that
the
higher
and
lower
byte
I/Os
(I/O[7:0]
and
I/O[15:8]
Document Number: 001-92576 Rev. *E
Page 5 of 21
5 Page 
CY7S1041G
CY7S1041GE
Switching Waveforms
Figure 9. Read Cycle No. 1 of CY7S1041G (Address Transition Controlled) [27, 28, 29]
tRC
ADDRESS
DATA I/O
tOHA
tAA
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 10. Read Cycle No. 2 of CY7S1041GE (Address Transition Controlled) [27, 28, 29]
ADDRESS
tRC
DATA I/O
ERR
tOHA
tAA
PREVIOUS DATAOUT
VALID
tOHA
tAA
PREVIOUS ERR VALID
DATAOUT VALID
ERR VALID
Notes
27. The device is continuously selected. OE = VIL, CE = VIL, BHE or BLE or both = VIL.
28. WE is HIGH for read cycle.
29. DS is HIGH for chip access.
Document Number: 001-92576 Rev. *E
Page 11 of 21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet CY7S1041G.PDF ] | |
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