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PDF CYBL11572 Data sheet ( Hoja de datos )
| Número de pieza | CYBL11572 | |
| Descripción | Programmable Radio-on-Chip | |
| Fabricantes | Cypress | |
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PRoC™ BLE: CYBL1XX7X
Family Datasheet
Programmable Radio-on-Chip With
Bluetooth Low Energy
General Description
PRoC™ BLE is a 32-bit, 48-MHz ARM® Cortex®-M0 BLE solution with CapSense®, 12-bit ADC, four timer, counter, pulse-width
modulators (TCPWM), Direct memory access (DMA), thirty-six GPIOs, two serial communication blocks (SCBs), LCD, and I2S.
PRoC BLE includes a royalty-free BLE stack compatible with Bluetooth® 4.2 and provides a complete, programmable, and flexible
solution for HID, remote controls, toys, beacons, and wireless chargers. In addition to these applications, PRoC BLE provides a
simple, low-cost way to add BLE connectivity to any system.
Features
Bluetooth® Smart Connectivity
■ Bluetooth 4.2 single-mode device
■ 2.4-GHz BLE radio and baseband with integrated balun
■ TX output power: –18 dBm to +3 dBm
■ Received signal strength indicator (RSSI) with 1-dB resolution
■ RX sensitivity: –92 dBm
■ TX current: 15.6 mA at 0 dBm
■ RX current: 16.4 mA
ARM Cortex-M0 CPU Core
■ 32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit
multiply, operating at up to 48 MHz
■ 256-KB flash memory
■ 32-KB SRAM memory
■ Emulated EEPROM using flash memory
■ Watchdog timer with dedicated internal low-speed oscillator
(ILO)
■ Eight-channel direct memory access (DMA) controller
Ultra-Low-Power
■ 1.5-µA Deep-Sleep mode with watch crystal oscillator (WCO)
on
■ 150-nA Hibernate mode current with SRAM retention
■ 60-nA Stop mode current with GPIO wakeup
CapSense® Touch Sensing with Two-Finger Gestures
■ Up to 36 capacitive sensors for buttons, sliders, and touchpads
■ One-finger gestures: finger tracking, scroll, inertial scroll,
edge-swipe, click, double-click
■ Two-finger gestures: scroll, inertial scroll, zoom-in, zoom-out
■ Cypress Capacitive Sigma-Delta (CSD) provides best-in-class
SNR (> 5:1) and liquid tolerance
■ Automatic hardware-tuning algorithm (SmartSense™)
Peripherals
■ 12-bit, 1-Msps SAR ADC with internal reference,
sample-and-hold (S/H), and channel sequencer
■ Ultra-low-power LCD segment drive for 128 segments with
operation in Deep-Sleep mode
■ Two serial communication blocks (SCBs) supporting I2C
(Master/Slave), SPI (Master/Slave), or UART
■ Four dedicated 16-bit TCPWMs
❐ Additional four 8-bit or two 16-bit PWMs
■ Programmable LVD from 1.8 V to 4.5 V
■ I2S Master interface
Clock, Reset, and Supply
■ Wide supply-voltage range: 1.9 V to 5.5 V
■ 3-MHz to 48-MHz internal main oscillator (IMO) with 2%
accuracy
■ 24-MHz external clock oscillator (ECO) without load
capacitance
■ 32-kHz WCO
Programmable GPIOs
■ 36 GPIOs configurable as open drain high/low,
pull-up/pull-down, HI-Z, or strong output
■ Any GPIO pin can be CapSense, LCD, or analog, with flexible
pin routing
Programming and Debug
■ 2-pin SWD
■ In-system flash programming support
Temperature and Packaging
■ Operating temperature range: –40 °C to +105 °C
■ Available in 56-pin QFN (7 mm × 7 mm) and 76-ball WLCSP
(3.52 mm × 3.91 mm) packages
PSoC® Creator™ Design Environment
■ Easy-to-use IDE to configure, develop, program, and test a
BLE application
■ Option to export the design to Keil, IAR, or Eclipse
Bluetooth Low Energy Protocol Stack
■ Bluetooth Low Energy protocol stack supporting generic
access profile (GAP) Central, Peripheral, Observer, or
Broadcaster roles
❐ Switches between Central and Peripheral roles on-the-go
■ Standard Bluetooth Low Energy profiles and services for
interoperability
❐ Custom profile and service for specific use cases
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-95464 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 16, 2016
1 page  
PRoC™ BLE: CYBL1XX7X
Family Datasheet
CPU Subsystem
CPU
The CYBL1XX7X device is based on an energy-efficient
ARM Cortex-M0 32-bit processor, offering low power
consumption, high performance, and reduced code size using
16-bit thumb instructions. The Cortex-M0’s ability to perform
single-cycle 32-bit arithmetic and logic operations, including
single-cycle 32-bit multiplication, helps in better performance.
The inclusion of the tightly-integrated Nested Vectored Interrupt
Controller (NVIC) with 32 interrupt lines enables the Cortex-M0
to achieve a low latency and a deterministic interrupt response.
The CPU also includes a 2-pin interface, the serial wire debug
(SWD), which is a 2-wire form of JTAG. The debug circuits are
enabled by default and can only be disabled in firmware. If
disabled, the only way to re-enable them is to erase the entire
device, clear flash protection, and reprogram the device with the
new firmware that enables debugging. In addition, it is possible
to use the debug pins as GPIO too. The device has four break-
points and two watchpoints for effective debugging.
Flash
The device has a 256-KB flash memory with a flash accelerator,
tightly coupled to the CPU to improve average access times from
flash. The flash is designed to deliver 1-wait-state (WS) access
time at 48 MHz and with 0-WS access time at 24 MHz. The flash
accelerator delivers 85% of single-cycle SRAM access
performance on average. Part of the flash can be used to
emulate EEPROM operation, if required.
During flash erase and programming operations (the maximum
erase and program time is 20 ms per row), the IMO will be set to
48 MHz for the duration of the operation. This also applies to the
emulated EEPROM. System design must take this into account
because peripherals operating from different IMO frequencies
will be affected. If it is critical that peripherals continue to operate
with no change during flash programming, always set the IMO to
48 MHz and derive the peripheral clocks by dividing down from
this frequency.
SRAM
The low-power 32-KB SRAM memory retains its contents even
in Hibernate mode.
ROM
The 8-KB supervisory ROM contains a library of executable
functions for flash programming. These functions are accessed
through supervisory calls (SVC) and enable in-system
programming of the flash memory.
DMA
DMA controller provides DataWrite (DW) and Direct Memory
Access (DMA). The DMA controller has following features
■ Supports up to 8 DMA channels with two independent
descriptors per channel
■ Four levels of priority for each channel
■ Byte, half-word (2 bytes), and word (4 bytes) transfers
■ Three modes of operation supported for each channel
■ Configurable interrupt generation
■ Output trigger on completion of transfer (transfer sizes up to
65536 data elements)
BLE Subsystem
The BLE subsystem consists of the link layer engine and
physical layer. The link layer engine supports both master and
slave roles. The link layer engine implements time-critical
functions such as encryption in the hardware to reduce the
power consumption, and provides minimal processor
intervention and a high performance. The key protocol elements,
such as host control interface (HCI) and link control, are
implemented in firmware. The direct test mode (DTM) is included
to test the radio performance using a standard Bluetooth tester.
The physical layer consists of a modem and an RF transceiver
that transmits and receives BLE packets at the rate of 1 Mbps
over the 2.4-GHz ISM band. In the transmit direction, this block
performs GFSK modulation and then converts the digital
baseband signal of these BLE packets into radio frequency
before transmitting them to air through an antenna. In the receive
direction, this block converts an RF signal from the antenna to a
digital bit stream after performing GFSK demodulation.
The RF transceiver contains an integrated balun, which provides
a single-ended RF port pin to drive a 50-Ω antenna terminal
through a pi-matching network. The output power is
programmable from –18 dBm to +3 dBm to optimize the current
consumption for different applications.
The Bluetooth Low Energy protocol stack uses the BLE
subsystem and provides the following features:
■ Link Layer (LL)
❐ Master and Slave roles
❐ 128-bit AES engine
❐ Encryption
❐ Low-duty-cycle advertising
❐ LE Ping
❐ LE Data Packet Length Extension (Bluetooth 4.2 feature)
❐ Link Layer Privacy (with extended scanning filter policy)
(Bluetooth 4.2 feature)
■ Bluetooth Low Energy 4.2 single-mode protocol stack with
logical link control and adaptation protocol (L2CAP), attribute
(ATT), and security manager (SM) protocols
■ Master and slave roles
■ API access to generic attribute profile (GATT), generic access
profile (GAP), and L2CAP
■ L2CAP connection-oriented channel
■ GAP features
❐ Broadcaster, Observer, Peripheral, and Central roles
❐ Security mode 1: Level 1, 2, 3, and 4
❐ Security mode 2: Level 1 and 2
❐ User-defined advertising data
❐ Multiple-bond support
■ GATT features
❐ GATT client and server
❐ Supports GATT subprocedures
❐ 32-bit universally unique identifiers (UUID)
■ Security Manager (SM)
❐ LE Secure Connections (Bluetooth 4.2 feature)
❐ Pairing methods: Just Works, Passkey Entry, Out of Band,
and Numeric Comparison
❐ Authenticated man-in-the-middle (MITM) protection and data
signing
■ Supports all SIG-adopted BLE profiles
Document Number: 001-95464 Rev. *J
Page 5 of 44
5 Page 
PRoC™ BLE: CYBL1XX7X
Family Datasheet
Table 2. CYBL1XX7X Pin List (WLCSP Package) (continued)
Pin
Name
Type
Description
C3
P2.2
GPIO
Port 2 Pin 2, analog/digital/lcd/csd
C4
P2.6
GPIO
Port 2 Pin 6, analog/digital/lcd/csd
C5
P3.0
GPIO
Port 3 Pin 0, analog/digital/lcd/csd
C6
P3.1
GPIO
Port 3 Pin 1, analog/digital/lcd/csd
C7
P3.2
GPIO
Port 3 Pin 2, analog/digital/lcd/csd
C8
XRES
RESET
Reset, active LOW
C9
P4.0
GPIO
Port 4 Pin 0, analog/digital/lcd/csd
D1 NC NC Do not connect
D2
P1.7
GPIO
Port 1 Pin 7, analog/digital/lcd/csd
D3
VDDA
POWER 1.71-V to 5.5-V analog supply
D4
P2.0
GPIO
Port 2 Pin 0, analog/digital/lcd/csd
D5
P2.1
GPIO
Port 2 Pin 1, analog/digital/lcd/csd
D6
P2.5
GPIO
Port 2 Pin 5, analog/digital/lcd/csd
D7
VSSD
GROUND Digital ground
D8
P4.1
GPIO
Port 4 Pin 1, analog/digital/lcd/csd
D9
P5.0
GPIO
Port 5 Pin 0, analog/digital/lcd/csd
E1 NC NC Do not connect
E2
P1.2
GPIO
Port 1 Pin 2, analog/digital/lcd/csd
E3
P1.3
GPIO
Port 1 Pin 3, analog/digital/lcd/csd
E4
P1.4
GPIO
Port 1 Pin 4, analog/digital/lcd/csd
E5
P1.5
GPIO
Port 1 Pin 5, analog/digital/lcd/csd
E6
P1.6
GPIO
Port 1 Pin 6, analog/digital/lcd/csd
E7
P2.4
GPIO
Port 2 Pin 4, analog/digital/lcd/csd
E8
P5.1
GPIO
Port 5 Pin 1, analog/digital/lcd/csd
E9
VSSD
GROUND Digital ground
F1 NC NC Do not connect
F2
VSSD
GROUND Digital ground
F3
P0.7
GPIO
Port 0 Pin 7, analog/digital/lcd/csd
F4
P0.3
GPIO
Port 0 Pin 3, analog/digital/lcd/csd
F5
P1.0
GPIO
Port 1 Pin 0, analog/digital/lcd/csd
F6
P1.1
GPIO
Port 1 Pin 1, analog/digital/lcd/csd
F7
VSSR
GROUND Radio ground
F8
VSSR
GROUND Radio ground
F9
VDDR
POWER 1.9-V to 5.5-V radio supply
G1 NC NC Do not connect
G2
P0.6
GPIO
Port 0 Pin 6, analog/digital/lcd/csd
G3
VDDD
POWER 1.71-V to 5.5-V digital supply
G4
P0.2
GPIO
Port 0 Pin 2, analog/digital/lcd/csd
G5
VSSD
GROUND Digital ground
G6
VSSR
GROUND Radio ground
Document Number: 001-95464 Rev. *J
Page 11 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CYBL11572.PDF ] | |
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